EP3C80 datasheet(150/274 Pages) ALTERA

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8–8

Chapter 8: External Memory Interfaces in the Cyclone III Device Family

Cyclone III Device Family Memory Interfaces Pin Support

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 1

f For more information about device package outline, refer to the Package and Thermal

Resistance page.

DQS

pins are listed in the Cyclone III and Cyclone III LS pin tables as DQSXY, in which X

indicates the DQS grouping number and Y indicates whether the group is located on

the top (T), bottom (B), left (L) or right (R) side of the device. Similarly, the

corresponding DQ pins are marked as DQXY, in which the X denotes the DQ grouping

number and Y denotes whether the group is located on the top (T), bottom (B), left (L)

or right (R) side of the device. For example, DQS2T indicates a DQS pin belonging to

group 2, located on the top side of the device. Similarly, the DQ pins belonging to that

group is shown as DQ2T.

1 Each DQ group is associated with its corresponding DQS pins, as defined in the Cyclone

III and Cyclone III LS pin tables; for example:

■

For DDR2 or DDR SDRAM, ×8 DQ group DQ3B[7:0] pins are associated with

the DQS3B pin (same 3B group index)

■

For QDR II SRAM, ×9 Q read-data group DQ3L[8..0] pins are associated with

DQS2L/CQ3L

and DQS3L/CQ3L# pins (same 3L group index)

The Quartus® II software issues an error message if a DQ group is not placed properly

with its associated DQS.

Figure 8–2 shows the location and numbering of the DQS, DQ, or CQ# pins in the

Cyclone III device family I/O banks.

1 For maximum timing performance, Altera recommends that the data groups for

external memory interfaces must always be within the same side of a device.

EP3C80 Datasheet(PDF) 150 Page - Altera Corporation