EP3C80 datasheet(153/274 Pages) ALTERA

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Chapter 8: External Memory Interfaces in the Cyclone III Device Family

8–11

Cyclone III Device Family Memory Interfaces Features

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Cyclone III Device Family Memory Interfaces Features

This section describes Cyclone III device family memory interfaces, including DDR

input registers, DDR output registers, OCT, and phase-lock loops (PLLs).

DDR Input Registers

The DDR input registers are implemented with three internal logic element (LE)

registers for every DQ pin. These LE registers are located in the logic array block (LAB)

adjacent to the DDR input pin.

Figure 8–4 shows Cyclone III device family DDR input registers.

The DDR data is first fed to two registers, input register AI and input register BI.

■

Input register AI captures the DDR data present during the rising edge of the clock

■

Input register BI captures the DDR data present during the falling edge of the clock

■

The data from the DDR input register is fed to two registers, sync_reg_h and

sync_reg_l

, then the data is typically transferred to a FIFO block to synchronize the

two data streams to the rising edge of the system clock. Because the read-capture

clock is generated by the PLL, the read-data strobe signal (DQS or CQ) is not used

during read operation in Cyclone III device family; hence, postamble is not a concern

in this case.

Figure 8–4. Cyclone III Device Family DDR Input Registers

dataout_h

dataout_l

Input Register B

Input Register A

neg_reg_out

DDR Input Registers in Cyclone III Device Family

Capture Clock

PLL

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