EP3C80 datasheet(152/274 Pages) ALTERA

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8–10

Chapter 8: External Memory Interfaces in the Cyclone III Device Family

Cyclone III Device Family Memory Interfaces Pin Support

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 1

In Cyclone III device family, the ×9 mode uses the same DQ and DQS pins as the ×8

mode, and one additional DQ pin that serves as a regular I/O pin in the ×8 mode. The

×18 mode uses the same DQ and DQS pins as ×16 mode, with two additional DQ pins

that serve as regular I/O pins in the ×16 mode. Similarly, the ×36 mode uses the same

and DQS pins as the ×32 mode, with four additional DQ pins that serve as regular

I/O pins in the ×32 mode. When not used as DQ or DQS pins, the memory interface pins

are available as regular I/O pins.

Optional Parity, DM, and Error Correction Coding Pins

Cyclone III device family supports parity in ×9, ×18, and ×36 modes. One parity bit is

available per eight bits of data pins. You can use any of the DQ pins for parity in

Cyclone III device family because the parity pins are treated and configured similar to

pins.

DM pins are only required when writing to DDR2 and DDR SDRAM devices.

QDR II SRAM devices use the BWS# signal to select the byte to be written into

memory. A low signal on the DM or BWS# pin indicates the write is valid. Driving the

DM or BWS# pin high causes the memory to mask the DQ signals. Each group of DQS

and DQ signals has one DM pin. Similar to the DQ output signals, the DM signals are

clocked by the -90° shifted clock.

In Cyclone III device family, the DM pins are preassigned in the device pinouts. The

Quartus II Fitter treats the DQ and DM pins in a DQS group equally for placement

purposes. The preassigned DQ and DM pins are the preferred pins to use.

Some DDR2 SDRAM and DDR SDRAM devices support error correction coding

(ECC), a method of detecting and automatically correcting errors in data

transmission. In 72-bit DDR2 or DDR SDRAM, there are eight ECC pins and 64 data

pins. Connect the DDR2 and DDR SDRAM ECC pins to a separate DQS or DQ group in

Cyclone III device family. The memory controller needs additional logic to encode

and decode the ECC data.

Address and Control/Command Pins

The address signals and the control or command signals are typically sent at a single

data rate. You can use any of the user I/O pins on all I/O banks of Cyclone III device

family to generate the address and control or command signals to the memory device.

1 Cyclone III device family does not support QDR II SRAM in the burst length of two.

Memory Clock Pins

In DDR2 and DDR SDRAM memory interfaces, the memory clock signals (CK and

CK#) are used to capture the address signals and the control or command signals.

Similarly, QDR II SRAM devices use the write clocks (K and K#) to capture the

address and command signals. The CK/CK# and K/K# signals are generated to

resemble the write-data strobe using the DDIO registers in Cyclone III device family.

f For more information about CK/CK# pins placement, refer to the “Pin Connection

Guidelines Tables” section in the Planning Pin and FPGA Resources chapter of the

External Memory Interface Handbook.

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