EP3C80 datasheet(173/274 Pages) ALTERA

173 / 274 page

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

9–15

Configuration Features

August 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

captures all its configuration data from the bitstream, it drives the nCEO pin low,

enabling the next device in the chain. You can leave the nCEO pin of the last device

unconnected or use it as a user I/O pin after configuration if the last device in the

chain is a Cyclone III device family. The nCONFIG, nSTATUS, CONF_DONE, DCLK, and

DATA[0]

pins of each device in the chain are connected (Figure 9–4).

The first Cyclone III device family in the chain is the configuration master and

controls the configuration of the entire chain. You must connect its MSEL pins to

select the AS configuration scheme. The remaining Cyclone III device family is

configuration slaves and you must connect their MSEL pins to select the PS

configuration scheme. Any other Altera device that supports PS configuration can

also be part of the chain as a configuration slave.

Figure 9–4. Multi-device AS Configuration

Notes to Figure 9–4:

(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.

(2) Connect the pull-up resistor to the VCCIO supply voltage of the I/O bank in which the nCE pin resides.

(3) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed the nCE pin of another device.

(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device of the Cyclone III device

family in AS mode and the slave devices in PS mode. To connect MSEL[3..0] for the master device in AS mode and slave devices in PS mode,

refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.

(5) These are dual-purpose I/O pins. The nCSO pin functions as the FLASH_NCE pin in AP mode. The ASDO pin functions as the DATA[1] pin in other

AP and FPP modes.

(6) Connect the series resistor at the near end of the serial configuration device.

(7) Connect the repeater buffers between the master and slave devices of the Cyclone III device family for DATA[0] and DCLK. All I/O inputs must

maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in

“Configuration and JTAG Pin I/O Requirements” on page 9–7.

(8) The 50-

 series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50- series

resistors if the 2.5- or 3.0-V configuration voltage standard is applied.

nSTATUS

nCONFIG

CONF_DONE

nCE

DATA[0]

DCLK

nCEO

MSEL[3..0]

DATA

DCLK

nCS

ASDI

N.C. (3)

(4)

Serial Configuration

Device

Slave Device of the Cyclone III Device Family

nSTATUS

nCONFIG

CONF_DONE

nCE

DATA[0]

DCLK

nCSO (5)

ASDO (5)

nCEO

MSEL[3..0]

(4)

VCCIO (1)

GND

VCCIO (1)

VCCIO (2)

(6)

VCCIO (1)

Buffers (7)

10 k

Ω (6), (8)

Ω(8)

Master Device of the

Cyclone III Device Family

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