EP3C80 datasheet(177/274 Pages) ALTERA

177 / 274 page

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family

9–19

Configuration Features

August 2012

Altera Corporation

Cyclone III Device Handbook

Volume 1

Single SRAM Object File

The second method configures both the master device and slave devices with the

same .sof. The serial configuration device stores one copy of the .sof. This setup is

shown in Figure 9–6 where the master is set up in AS mode and the slave devices are

set up in PS mode. You must set up one or more slave devices in the chain. All the

slave devices must be set up as shown in Figure 9–6.

In this setup, all the Cyclone III device family in the chain are connected for

concurrent configuration. This can reduce the AS configuration time because all the

Cyclone III device family is configured in one configuration cycle. Connect the nCE

input pins of all the Cyclone III device family to ground. You can either leave the nCEO

output pins on all the Cyclone III device family unconnected or use the nCEO output

pins as normal user I/O pins. The DATA and DCLK pins are connected in parallel to all

the Cyclone III device family.

Figure 9–6. Multi-Device AS Configuration where the Devices Receive the Same Data with a Single .sof

Notes to Figure 9–6:

(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.

(2) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.

(3) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device of the Cyclone III device

family in AS mode and the slave devices in PS mode. To connect MSEL[3..0] for the master device in AS mode and slave devices in PS mode,

refer to Table 9–7 on page 9–11. Connect the MSEL pins directly to VCCA or GND.

(4) These are dual-purpose I/O pins. The nCSO pin functions as the FLASH_NCE pin in AP mode. The ASDO pin functions as the DATA[1] pin in other

AP and FPP modes.

(5) Connect the series resistor at the near end of the serial configuration device.

(6) Connect the repeater buffers between the master and slave devices for DATA[0] and DCLK. All I/O inputs must maintain a maximum AC voltage

of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in “Configuration and JTAG Pin I/O

Requirements” on page 9–7.

(7) The 50-

 series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50- series

resistors if the 2.5- or 3.0-V configuration voltage standard is applied.

nSTATUS

nCONFIG

CONF_DONE

nCE

DATA[0]

DCLK

nCEO

MSEL[3..0]

N.C. (2)

(3)

nSTATUS

nCONFIG

CONF_DONE

nCE

DATA[0]

DCLK

nCEO

MSEL[3..0]

N.C. (2)

(3)

nSTATUS

nCONFIG

CONF_DONE

nCE

DATA[0]

DCLK

nCSO (4)

ASDO (4)

nCEO

MSEL[3..0]

(3)

DATA

DCLK

nCS

ASDI

Serial Configuration

Device

GND

N.C. (2)

VCCIO (1)

Buffers (6)

10 k

(5)

(7)

(5),(7)

Slave Device 2 of the Cyclone III

Device Family

Slave Device 1 of the Cyclone III

Device Family

Master Device of the Cyclone III

Device Family

EP3C80 Datasheet(PDF) 177 Page - Altera Corporation

EP3C80 Datasheet(HTML) 177 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL