AD8021 datasheet(5/28 Pages) AD

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AD7986

Rev. B | Page 5 of 28

TIMING SPECIFICATIONS

AVDD = DVDD = 2.5 V, BVDD = 5 V, VIO = 1.8 V to 2.7 V, VREF = 4.096 V, TA = −40°C to +85°C, unless otherwise noted.1

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

Conversion Time: CNV Rising Edge to Data Available (Turbo Mode/Normal Mode)

CONV

400/500

Acquisition Time

ACQ

100

Time Between Conversions (Turbo Mode/Normal Mode)

CYC

500/660

CNV Pulse Width (CS Mode)

CNVH

Data Read During Conversion (Turbo Mode/Normal Mode)

DATA

200/300

Quiet Time During Acquisition from Last SCK Falling Edge to CNV Rising Edge

QUIET

SCK Period (CS Mode)

SCK

SCK Period (Chain Mode)

SCK

SCK Low Time

SCKL

3.5

SCK High Time

SCKH

3.5

SCK Falling Edge to Data Remains Valid

HSDO

SCK Falling Edge to Data Valid Delay

DSDO

CNV or SDI Low to SDO D17 MSB Valid (CS Mode)

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)

DIS

SDI Valid Setup Time from CNV Rising Edge

SSDICNV

SDI Valid Hold Time from CNV Rising Edge (CS Mode)

HSDICNV

SDI Valid Hold Time from CNV Rising Edge (Chain Mode)

HSDICNV

SCK Valid Setup Time from CNV Rising Edge (Chain Mode)

SSCKCNV

SCK Valid Hold Time from CNV Rising Edge (Chain Mode)

HSCKCNV

SDI Valid Setup Time from SCK Falling Edge (Chain Mode)

SSDISCK

SDI Valid Hold Time from SCK Falling Edge (Chain Mode)

HSDISCK

SDI High to SDO High (Chain Mode with Busy Indicator)

DSDOSDI

1 See Figure 2 and Figure 3 for load conditions.

500µA

IOL

500µA

IOH

1.4V

TO SDO

20pF

Figure 2. Load Circuit for Digital Interface Timing

90% VIO

10% VIO

VIH1

VIL1

VIH1

tDELAY

1MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS

SPECIFICATIONS IN TABLE 3.

Figure 3. Voltage Levels for Timing

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