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DM163006 Datasheet(PDF) 227 Page - Microchip Technology |
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DM163006 Datasheet(HTML) 227 Page - Microchip Technology |
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227 / 320 page ![]() 2001 Microchip Technology Inc. Advance Information DS39541A-page 227 PIC18C601/801 BRA Unconditional Branch Syntax: [ label ] BRA n Operands: -1024 ≤ n ≤ 1023 Operation: (PC) + 2 + 2n → PC Status Affected: None Encoding: 1101 0nnn nnnn nnnn Description: Add the 2’s complement number ’2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two- cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ’n’ Process Data Write to PC No operation No operation No operation No operation Example: HERE BRA Jump Before Instruction PC = address (HERE) After Instruction PC = address (Jump) BSF Bit Set f Syntax: [ label ] BSF f, b [,a] Operands: 0 ≤ f ≤ 255 0 ≤ b ≤ 7 a ∈ [0,1] Operation: 1 → f<b> Status Affected: None Encoding: 1000 bbba ffff ffff Description: Bit 'b' in register 'f' is set. If ’a’ is 0 Access Bank will be selected, over- riding the BSR value. If ’a’ is 1, the Bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ’f’ Process Data Write register ’f’ Example: BSF FLAG_REG, 7 Before Instruction FLAG_REG = 0Ah After Instruction FLAG_REG = 8Ah |
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