DM163006 datasheet(27/320 Pages) MICROCHIP

27 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 27

PIC18C601/801

If the main oscillator is configured for HS4 (PLL) mode

with SCS1 bit set to ‘1’, an oscillator start-up time

(TOST), plus an additional PLL time-out (TPLL) will

occur. The PLL time-out is typically 2 ms and allows the

PLL to lock to the main oscillator frequency. A timing

diagram indicating the transition from the Timer1 oscil-

lator to the main oscillator for HS4 mode is shown in

Figure 2-8.

If the main oscillator is configured for HS4 (PLL) mode,

with SCS1 bit set to ‘0’, only oscillator start-up time

(TOST) will occur. Since SCS1 bit is set to ‘0’, PLL out-

put is not used, so the system oscillator will come from

OSC1 directly and additional delay of TPLL is not

required. A timing diagram indicating the transition from

the Timer1 oscillator to the main oscillator for HS4

mode is shown in Figure 2-9.

If the main oscillator is configured in the RC or EC

modes, there is no oscillator start-up time-out. Opera-

tion will resume after eight cycles of the main oscillator

have been counted. A timing diagram indicating the

transition from the Timer1 oscillator to the main oscilla-

tor for RC and EC modes is shown in Figure 2-10.

FIGURE 2-8:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS4 WITH SCS1 = 1)

FIGURE 2-9:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS4 WITH SCS = 0)

Q2 Q3 Q4

Q1 Q2

OSC1

Internal System

SCS0

(OSCCON<0>)

Program Counter

PC + 2

Note: TOST = 1024TOSC (drawing not to scale).

T1OSI

Clock

TOST

PC + 4

TPLL

TOSC

TT1P

TSCS

OSC2

PLL Clock

Input

OSC1

Internal

SCS0

(OSCCON<0>)

Program

PC + 2

Note:

TOST = 1024TOSC (drawing not to scale).

T1OSI

Clock

PLL

TOST

PC + 4

TPLL

TOSC

TDLY

TT1P

OSC2

Output

Counter

System

Clock

TSCS

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