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DM163006 Datasheet(PDF) 23 Page - Microchip Technology |
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DM163006 Datasheet(HTML) 23 Page - Microchip Technology |
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23 / 320 page ![]() 2001 Microchip Technology Inc. Advance Information DS39541A-page 23 PIC18C601/801 2.4 External Clock Input The EC oscillator mode requires an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is no oscillator start-up time required after a Power-on Reset or after a recovery from SLEEP mode. In the EC oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 shows the pin connections for the EC oscillator mode. FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (EC OSC CONFIGURATION) 2.5 HS4 (PLL) A Phase Lock Loop (PLL) circuit is provided as a soft- ware programmable option for users that want to multi- ply the frequency of the incoming crystal oscillator signal by 4. For an input clock frequency of 6 MHz, the internal clock frequency will be multiplied to 24 MHz. This is useful for customers who are concerned with EMI due to high frequency crystals. The PLL is enabled by configuring HS oscillator mode and setting the PLLEN bit in the OSCON register. If HS oscillator mode is not selected, or PLLEN bit in OSCCON register is clear, the PLL is not enabled and the system clock will come directly from OSC1. HS oscillator mode is the default for PIC18C601/801. In all other modes, the PLLEN bit and the SCS1 bit are forced to ‘0’. A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out, referred to as TPLL. FIGURE 2-4: PLL BLOCK DIAGRAM OSC1 OSC2 FOSC/4 Clock from ext. system PIC18C601/801 VCO Loop Filter Feedback Divider 32 10 Crystal Osc OSCOUT OSCIN PLL Enable FIN FOUT SYSCLK Phase Comparator CVCO HS Osc |
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