DM163006 datasheet(81/320 Pages) MICROCHIP

81 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 81

PIC18C601/801

6.3.3

EXTERNAL TABLE WRITE IN 16-BIT

WORD WRITE MODE

This mode allows Table Writes to any type of word-

wide external memories.

This method makes a distinction between TBLWT

cycles to even or odd addresses.

During a TBLWT cycle to an even address, where

TBLPTR<0> = 0, the TABLAT data is transferred to a

holding latch and the external address data bus is tri-

stated for the data portion of the bus cycle. No write

signals are activated.

During a TBLWT cycle to an odd address, where

TBLPTR<0> = 1, the TABLAT data is presented on the

upper byte of the AD<15:0> bus. The contents of the

holding latch are presented on the lower byte of the

AD<15:0> bus.

The WRH line is strobed for each

write cycle and the WRL line is unused. The BA0 line

indicates the LSb of TBLPTR, but it is unnecessary.

The UB and LB lines are active to select both bytes.

The obvious limitation to this method is that the TBLWT

must be done in pairs on a specific word boundary to

correctly write a word location.

Figure 6-9 shows the timing associated with this mode.

FIGURE 6-9:

TBLWT

EXTERNAL INTERFACE TIMING (16-BIT WORD WRITE MODE)

Q3 Q4

ALE

WRH

WRL

BA0

Opcode Fetch

TBLWT*+

TBLWT* Cycle1

MOVLW 55h

from 007554h

Q3 Q4

TBLWT 56h

to 199E66h

from 00755Ah

Memory

Cycle

Instruction

Execution

INST(PC-2)

TBLWT* Cycle2

MOVWF TABLAT

from 007556h

Q3 Q4

TBLWT 92h

to 199E67h

TBLWT*+ Cycle1 TBLWT*+ Cycle2

Opcode Fetch

TBLWT*

from 007558h

MOVWF

’1’

A<19:16>

3AAAh

AD<15:0>

000Dh

CF33h

3AABh

6FF4h

3AACh

000Ch

3AADh

0E55h

CF33h

9256h

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