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DM163006 Datasheet(PDF) 313 Page - Microchip Technology

Part # DM163006
Description  High-Performance ROM-less Microcontrollers
PDF  320 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DM163006 Datasheet(HTML) 313 Page - Microchip Technology

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 2001 Microchip Technology Inc.
Advance Information
DS39541A-page 313
PIC18C601/801
SSP .................................................................................. 149
Block Diagram
SPI Mode ......................................................... 153
Block Diagram (SPI Mode) ...................................... 153
I2C Mode. See I2C
SPI Mode ................................................................. 153
SPI Mode. See SPI
SSPBUF .................................................................. 155
SSPCON1 ............................................................... 151
SSPCON2 ............................................................... 152
SSPSR .................................................................... 155
SSPSTAT ................................................................ 150
TMR2 Output for Clock Shift ........................... 135
, 136
SSP Module
SPI Master Mode ..................................................... 155
SPI Slave Mode ....................................................... 156
SSPCON1 Register ......................................................... 151
SSPCON2 Register ......................................................... 152
SSPOV ............................................................................ 167
SSPSTAT Register .......................................................... 150
R/W Bit .................................................................... 160
SUBFWB ................................................................ 250
, 251
SUBLW ............................................................................ 251
SUBWF ............................................................................ 252
SUBWFB ......................................................................... 253
SWAPF ............................................................................ 254
Synchronous Serial Port. See SSP
T
Table Pointer Register ....................................................... 74
Table Read ........................................................................ 75
Table Read/Write Control Registers .................................. 74
Table Write ........................................................................ 77
16-bit External
16-bit Word Write Mode ..................................... 81
Byte Select Mode .............................................. 82
Byte Write Mode ................................................ 80
8-bit External ............................................................. 78
Table Writes
Long Writes ............................................................... 83
TBLRD ............................................................................. 255
TBLWT ............................................................................. 256
Timer0 .............................................................................. 127
Associated Registers ............................................... 129
Block Diagram
16-bit Mode ...................................................... 128
8-bit Mode ........................................................ 128
Clock Source Edge Select (T0SE Bit) ..................... 129
Clock Source Select (T0CS Bit) .............................. 129
Interrupt ................................................................... 101
Overflow Interrupt .................................................... 129
Prescaler. See Prescaler, Timer0
T0CON Register ...................................................... 127
Timing Diagram ....................................................... 281
Timer1 .............................................................................. 130
Associated Registers ............................................... 134
Block Diagram ......................................................... 131
16-bit R/W Mode .............................................. 132
Oscillator ......................................................... 130
, 133
Overflow Interrupt ........................................... 130
, 133
Prescaler. See Prescaler, Timer1
Special Event Trigger (CCP) ...........................133
, 144
T1CON Register ...................................................... 130
Timing Diagram ....................................................... 281
TMR1H Register ..................................................... 130
TMR1L Register ...................................................... 130
TMR3L Register ...................................................... 137
Timer2
Associated Registers .............................................. 136
Block Diagram ......................................................... 136
Postscaler. See Postscaler, Timer2
PR2 Register ...................................................135
, 146
Prescaler. See Prescaler, Timer2
SSP Clock Shift ...............................................135
, 136
T2CON Register ...................................................... 135
TMR2 Register ........................................................ 135
TMR2 to PR2 Match Interrupt ................ 135
, 136, 146
Timer3 ............................................................................. 137
Associated Registers .............................................. 139
Block Diagram ......................................................... 138
16-bit R/W Mode ............................................. 138
Oscillator .........................................................137
, 139
Overflow Interrupt ............................................137
, 139
Special Event Trigger (CCP) ................................... 139
T3CON Register ...................................................... 137
TMR3H Register ..................................................... 137
Timing Diagrams
Acknowledge Sequence Timing .............................. 170
Baud Rate Generator with Clock Arbitration ........... 165
BRG Reset Due to SDA Collision ........................... 174
Bus Collision
START Condition Timing ................................ 173
Bus Collision During a RESTART Condition
(Case 1) .................................................. 175
Bus Collision During a RESTART Condition
(Case 2) .................................................. 175
Bus Collision During a START Condition
(SCL = 0) ................................................. 174
Bus Collision During a STOP Condition .................. 176
Bus Collision for Transmit and Acknowledge .......... 172
I2C Bus Data ........................................................... 289
I2C Master Mode First START Bit Timing ............... 165
I2C Master Mode Reception Timing ........................ 169
I2C Master Mode Transmission Timing ................... 168
Master Mode Transmit Clock Arbitration ................. 171
Repeated START Condition .................................... 166
Slave Synchronization ............................................. 156
Slow Rise Time ......................................................... 33
SPI Mode Timing (Master Mode) SPI Mode
Master Mode Timing Diagram ......................... 155
SPI Mode Timing (Slave Mode with CKE = 0) ........ 157
SPI Mode Timing (Slave Mode with CKE = 1) ........ 157
STOP Condition Receive or Transmit ..................... 170
Time-out Sequence on Power-up ............................. 32
USART Asynchronous Master Transmission .......... 184
USART Asynchronous Reception ........................... 186
USART Synchronous Reception ............................. 189
USART Synchronous Transmission ........................ 188
Wake-up from SLEEP via Interrupt ......................... 213



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