DM163006 datasheet(139/320 Pages) MICROCHIP

139 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 139

PIC18C601/801

13.2

Timer1 Oscillator

The Timer1 oscillator may be used as the clock source

for Timer3. The Timer1 oscillator is enabled by setting

the T1OSCEN bit (T1CON Register). The oscillator is

a low power oscillator rated up to 200 kHz. Refer to

“Timer1 Module”, Section 11.0, for Timer1 oscillator

details.

13.3

Timer3 Interrupt

The TMR3 register pair (TMR3H:TMR3L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR3 interrupt, if enabled, is generated on overflow,

which is latched in interrupt flag bit TMR3IF (PIE

registers). This interrupt can be enabled/disabled by

setting/clearing TMR3 interrupt enable bit TMR3IE

(PIE registers).

13.4

Resetting Timer3 Using a CCP

Trigger Output

If the CCP module is configured in Compare mode to

generate a “special event trigger" (CCP1M3:CCP1M0

= 1011), this signal will reset Timer3.

Timer3 must be configured for either Timer, or Synchro-

nized Counter mode, to take advantage of this feature. If

Timer3 is running in Asynchronous Counter mode, this

RESET operation may not work. In the event that a write

to Timer3 coincides with a special event trigger from

CCP1, the write will take precedence. In this mode of

operation,

the

CCPR1H:CCPR1L

registers

pair

becomes the period register for Timer3. Refer to

Section 14.0, “Capture/Compare/PWM (CCP) Modules”,

for CCP details.

TABLE 13-1:

REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Note:

The special event triggers from the CCP

module will not set interrupt flag bit

TMR3IF (PIR registers).

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

RESETS

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 000x

0000 000u

PIR2

—

BCLIF

LVDIF

TMR3IF

CCP2IF

---- 0000

-0-- 0000

PIE2

—

BCLIE

LVDIE

TMR3IE

CCP2IE

---- 0000

-0-- 0000

IPR2

—

BCLIP

LVDIP

TMR3IP

CCP2IP

---- 0000

-0-- 0000

TMR3L

Holding register for the Least Significant Byte of the 16-bit TMR3 register

xxxx xxxx

uuuu uuuu

TMR3H

Holding register for the Most Significant Byte of the 16-bit TMR3 register

xxxx xxxx

uuuu uuuu

T1CON

RD16

—

T1CKPS1 T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

0-00 0000

u-uu uuuu

T3CON

RD16

T3CCP2 T3CKPS1 T3CKPS0

T3CCP1

T3SYNC

TMR3CS

TMR3ON

0000 0000

uuuu uuuu

Legend:

= unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer3 module.

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