DM163006 datasheet(170/320 Pages) MICROCHIP

170 / 320 page

PIC18C601/801

DS39541A-page 170

Advance Information

 2001 Microchip Technology Inc.

15.4.10

ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence enable bit, ACKEN (SSPCON2

and the contents of the Acknowledge Data bit (ACKDT)

is presented on the SDA pin. If the user wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The baud rate gen-

erator then counts for one rollover period (TBRG) and the

SCL pin is de-asserted (pulled high). When the SCL pin

is sampled high (clock arbitration), the baud rate gener-

ator counts for TBRG. The SCL pin is then pulled low. Fol-

lowing this, the ACKEN bit is automatically cleared, the

baud rate generator is turned off and the MSSP module

then goes into IDLE mode (Figure 15-17).

15.4.10.1 WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the con-

tents of the buffer are unchanged (the write doesn’t occur).

15.4.11

STOP CONDITION TIMING

A STOP bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN (SSPCON2 register). At the end of a receive/

transmit, the SCL line is held low after the falling edge

of the ninth clock. When the PEN bit is set, the master

will assert the SDA line low. When the SDA line is sam-

pled low, the baud rate generator is reloaded and

counts down to 0. When the baud rate generator times

out, the SCL pin will be brought high, and one TBRG

(baud rate generator rollover count) later, the SDA pin

will be de-asserted. When the SDA pin is sampled high

while SCL is high, the P bit (SSPSTAT register) is set.

A TBRG later, the PEN bit is cleared and the SSPIF bit

is set (Figure 15-18).

15.4.11.1

WCOL Status Flag

If the user writes the SSPBUF when a STOP sequence

is in progress, then the WCOL bit is set and the contents

of the buffer are unchanged (the write doesn’t occur).

FIGURE 15-17:

ACKNOWLEDGE SEQUENCE WAVEFORM

FIGURE 15-18:

STOP CONDITION RECEIVE OR TRANSMIT MODE

Note: TBRG = one baud rate generator period.

SDA

SCL

Set SSPIF at the end

Acknowledge sequence starts here,

Write to SSPCON2

ACKEN automatically cleared

Cleared in

TBRG

of receive

ACK

ACKEN = 1, ACKDT = 0

SSPIF

software

Set SSPIF at the end

of Acknowledge sequence

Cleared in

software

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSPCON2

Set PEN

Falling edge of

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

9th clock

SCL brought high after TBRG

TBRG

after SDA sampled high, P bit (SSPSTAT) is set

TBRG

to set up STOP condition

ACK

TBRG

PEN bit (SSPCON2) is cleared by

hardware and the SSPIF bit is set

Note:

TBRG = one baud rate generator period.

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