PCM1750P datasheet(7/21 Pages) TI

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PCM1750

tions of the PCM1750. Two other switched-capacitor TDACs

(trim-DACs, which employ laser-trimmed nichrome resis-

tors) are also used to provide small correction voltages to the

latching comparators. These small correction voltages com-

pensate for ratio matching errors of the binary-weighted

capacitors in the CDAC. The comparators contain autozeroed

preamplifier stages ahead of the latching amplifier stage to

produce a one bit, serial data stream that controls the

successive approximation algorithm for each channel of the

PCM1750.

To simplify user application, the PCM1750 includes an

internal band-gap reference with fast settling buffer amplifi-

ers to drive the CDACs. The dual converters operate syn-

chronously (to minimize digital noise conversion errors)

using an external system clock (normally at 1X, 2X or 4X

the standard 48kHz audio sampling rate). By operating at a

2X or 4X oversampling rate the roll-off requirement for the

input anti-aliasing filters is relaxed. For example, 1X sys-

tems typically use a 9 to 11 pole LPF (low pass filter)

whereas a 4X system can use a 6th (or smaller) order filter

when an appropriate digital filter such as the DF1750 is used

in conjunction with the sampling system. Oversampling also

has the added benefit of improved signal to noise ratio and

total harmonic distortion. Two serial outputs, one for each

input channel, provide binary-two’s-complement coded out-

put to an optional external digital decimation filter when

over sampling operation is desired. The use of the optional

companion digital filter, the DF1750, is described later in

the installation and application sections of this product data

sheet. A separate product data sheet is also available for the

Burr-Brown DF1750 giving all the specifications and per-

formance diagrams associated with this digital filter.

SAMPLE (TRACKING) MODE

After each conversion, the dual ADC returns to the SAMPLE

mode in order to track the input signals. The switches shown

in the simplified circuit diagram of Figure 1 will then be in

the following states: S1 connects VIN to C1 ; S2 to S18

connect C2 to C18 to VREF; H1 and H2 connect the top

plates of the capacitor arrays to analog common; and the

latching comparator is switched into its auto-zero mode by

closing AZ1 to AZ4. Notice that C1 serves two purposes: it

samples and stores the input signal VIN and it is the MSB of

the CDAC. Storing VREF on C2 to C18 creates a bipolar

offset, enabling VIN to cover a span from –VREF to +VREF.

The 1/f noise as well as the DC input offset voltage of the

comparator are removed by an autozeroing cycle which

* Clock from optional digital filter chip (DF1750 4x decimation filter).

P11 (CONVERT)

P4 (EXT CLK IN)

*Master

System

Clock

64 1 2

3 4 5 6 7 8 9 101112 13 14 15 16

50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2

Bit 1

MSB

Bit 2

Bit 3

Bit 16

Bit 17

Bit 1

MSB

Bit 2

Bit 3

Bit 16

Bit 17

Bit 4

Bit 18

LSB

Bit 18

LSB

INTERNAL

S/H

CONTROL

SR1

SR2

SR3

P3 (SOUT L)

P12 (SOUT R)

Bit 3 test time

Bit 2 test time

Bit 1 test time

HOLD

SAMPLE

FIGURE 2. PCM1750 Input/Output Timing Diagram.

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