PCM1750P datasheet(12/21 Pages) TI

12 / 21 page

PCM1750

plots are shown at four different input signal levels (with and

without a 4X decimation filter): 0dB, –20dB, –40dB, and –

60dB.

CHANNEL SEPARATION

To test channel separation a 1kHz signal sampled at 192kHz

is placed on one input of the PCM1750 while the other input

is held at 0V. An FFT is performed on the idle (0V) channel

and the result checked to insure that the 1kHz tone is

suppressed by a minimum of 96dB.

GAIN AND OFFSET ERRORS

Initial gain and bipolar offset errors are laser trimmed at the

wafer level and 100% final tested to insure compliance with

the electrical specifications. Bipolar offset errors can be

further reduced to zero by using the optional offset adjust-

ment circuitry shown in the connection diagram (Figure 7).

Gain errors can be adjusted by varying VREF to either

channel of the converter. This is accomplished by either

using an adjustable external reference or by placing buffer

amplifiers with adjustable gain between VREFOUT and

VREFIN as shown in Figure 8a.

INTEGRAL AND DIFFERENTIAL LINEARITY

DC Linearity Testing

The absolute linearity of the PCM1750 is on the order of 15

bits or more as can be seen from the THD versus Frequency

plots in the Typical Performance Curves. Not every code in

the converter must be 15-bit linear to achieve the specified

THD+N performance, but a very high percentage will be

that linear. The same observation also applies to differential

linearity errors in the PCM1750. Because the PCM1750 is

not 100% tested for DC linearity specifications, no mini-

mum or maximum specifications are given for integral or

differential linearity errors.

No Missing Codes Operation

A no missing codes specification is not given for the

PCM1750 for the same reasons as given above. The

PCM1750, however, typically has fewer than 16 codes (less

than 0.01%) missing at a 14-bit resolution level. A 100% no

missing codes specification cannot be maintained above the

12-bit level, although this has very little impact on overall

dynamic performance (THD+N). The few missing codes

that do occur at higher resolution levels are at the bit-2 and

lower major carry transitions of the converter. There are

typically no missing codes (at 14 bits) around the critical

bipolar zero operation zone (

±1/8 of full scale range around

bipolar zero or 0V). The critical bipolar differential linearity

error can be reduced from its initial value to zero using the

optional MSB adjustment circuitry shown in the connection

diagram (Figure 7).

REFERENCE

The gain drift of the PCM1750 is primarily due to the drift

associated with the reference. Better drift performance can

be achieved using an external reference like the ones ex-

plained in the applications section (Figures 8b, 8c). The

Typical Performance Curves plot of VREF Output versus

Temperature shows the full range of operation including

initial error and typical gain drift. Pertinent performance

data are found in the electrical specification table.

Reference Bypass

Both P18 and P25 (VREFIN) should be bypassed with a

µF to 47µF tantalum capacitor. If there are important

system reasons for using the PCM1750 reference externally,

the outputs of P19 and P24 must be appropriately buffered,

and bypassed (see Figure 8).

FIGURE 6. PCM1750 Production Test Setup.

PCM1750

Low Pass

Filter

FTT

Analyzer

High

Accuracy

Sine Wave

Generator

Timing

Control

f = 192kHz

f = 1kHz

Serial Data Left

Serial Data Right

VINL

INR

Parametric

Tester

PCM1750P Datasheet(PDF) 12 Page - Texas Instruments

PCM1750P Datasheet(HTML) 12 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Datasheet Download

Link URL