74HC595DB datasheet(5/24 Pages) NXP

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74HC_HCT595

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Product data sheet

Rev. 6 — 12 December 2011

5 of 24

NXP Semiconductors

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches;

3-state

6.2 Pin description

Functional description

[1]

H = HIGH voltage state;

L = LOW voltage state;

 = LOW-to-HIGH transition;

X = don’t care;

NC = no change;

Z = high-impedance OFF-state.

Table 2.

Pin description

Symbol

Description

parallel data output 1

parallel data output 2

parallel data output 3

parallel data output 4

parallel data output 5

parallel data output 6

parallel data output 7

GND

ground (0 V)

Q7S

serial data output

master reset (active LOW)

SHCP

shift register clock input

STCP

storage register clock input

output enable input (active LOW)

serial data input

parallel data output 0

VCC

supply voltage

Table 3.

Function table[1]

Control

Input

Output

Function

SHCP STCP OE

Q7S

a LOW-level on MR only affects the shift registers



empty shift register loaded into storage register

shift register clear; parallel outputs in high-impedance OFF-state



Q6S

logic HIGH-level shifted into shift register stage 0. Contents of all

shift register stages shifted through, e.g. previous state of stage 6

(internal Q6S) appears on the serial output (Q7S).



QnS

contents of shift register stages (internal QnS) are transferred to

the storage register and parallel output stages



Q6S

QnS

contents of shift register shifted through; previous contents of the

shift register is transferred to the storage register and the parallel

output stages

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