74HC595DB datasheet(6/24 Pages) NXP

6 / 24 page

74HC_HCT595

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 12 December 2011

6 of 24

NXP Semiconductors

74HC595; 74HCT595

8-bit serial-in, serial or parallel-out shift register with output latches;

3-state

Limiting values

[1]

For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.

[2]

For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.

[3]

For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.

[4]

For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.

Fig 8.

Timing diagram

SHCP

STCP

Q7S

Z-state

mna556

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

0.5

IIK

input clamping current

VI < 0.5 V or VI >VCC + 0.5 V

20

IOK

output clamping current

VO < 0.5 V or VO > VCC + 0.5 V

20

output current

VO = 0.5 V to (VCC +0.5 V)

pin Q7S

25

pins Qn

35

ICC

supply current

IGND

ground current

70

Tstg

storage temperature

65

+150

C

Ptot

total power dissipation

DIP16 package

[1] -

750

SO16 package

[2] -

500

SSOP16 package

[3] -

500

TSSOP16 package

[3] -

500

DHVQFN16 package

[4] -

500

74HC595DB Datasheet(PDF) 6 Page - NXP Semiconductors

74HC595DB Datasheet(HTML) 6 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL