LPC2142 datasheet(11/45 Pages) NXP

11 / 45 page

LPC2141_42_44_46_48

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Product data sheet

Rev. 5 — 12 August 2011

11 of 45

NXP Semiconductors

LPC2141/42/44/46/48

Single-chip 16-bit/32-bit microcontrollers

P1.23/

PIPESTAT2

36[6]

I/O

P1.23 — General purpose input/output digital pin (GPIO). Standard

I/O port with internal pull-up.

PIPESTAT2 — Pipeline Status, bit 2.

P1.24/

TRACECLK

32[6]

I/O

P1.24 — General purpose input/output digital pin (GPIO). Standard

I/O port with internal pull-up.

TRACECLK — Trace Clock.

P1.25/EXTIN0

28[6]

I/O

P1.25 — General purpose input/output digital pin (GPIO). Standard

I/O port with internal pull-up.

EXTIN0 — External Trigger Input.

P1.26/RTCK

24[6]

I/O

P1.26 — General purpose input/output digital pin (GPIO).

I/O

RTCK — Returned Test Clock output. Extra signal added to the JTAG

port. Assists debugger synchronization when processor frequency

varies. Bidirectional pin with internal pull-up.

Note: LOW on RTCK while RESET is LOW enables pins P1[31:26] to

operate as Debug port after reset.

P1.27/TDO

64[6]

I/O

P1.27 — General purpose input/output digital pin (GPIO).

TDO — Test Data out for JTAG interface.

P1.28/TDI

60[6]

I/O

P1.28 — General purpose input/output digital pin (GPIO).

TDI — Test Data in for JTAG interface.

P1.29/TCK

56[6]

I/O

P1.29 — General purpose input/output digital pin (GPIO).

TCK — Test Clock for JTAG interface. This clock must be slower than



6 of the CPU clock (CCLK) for the JTAG interface to operate.

P1.30/TMS

52[6]

I/O

P1.30 — General purpose input/output digital pin (GPIO).

TMS — Test Mode Select for JTAG interface.

P1.31/TRST

20[6]

I/O

P1.31 — General purpose input/output digital pin (GPIO).

TRST — Test Reset for JTAG interface.

D+

10[7]

I/O

USB bidirectional D+ line.



11[7]

I/O

USB bidirectional D

 line.

RESET

57[8]

External reset input: A LOW on this pin resets the device, causing

I/O ports and peripherals to take on their default states, and processor

execution to begin at address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

62[9]

Input to the oscillator circuit and internal clock generator circuits.

XTAL2

61[9]

Output from the oscillator amplifier.

RTCX1

3[9][10]

Input to the RTC oscillator circuit.

RTCX2

5[9][10]

Output from the RTC oscillator circuit.

VSS

6, 18, 25, 42,

Ground: 0 V reference.

VSSA

Analog ground: 0 V reference. This should nominally be the same

voltage as VSS, but should be isolated to minimize noise and error.

VDD

23, 43, 51

3.3 V power supply: This is the power supply voltage for the core and

I/O ports.

Table 3.

Pin description …continued

Symbol

Type

Description

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