AD9863

Rev. A | Page 27 of 40

Table 14. Mode Pin Names and Descriptions

Pin Name

Description

ADC_LO_PWR

ADC Low Power Mode Option. ADC_LO_PWR is latched during the rising edge of RESET.

Logic low results in ADC operation at nominal power mode.

Logic high results in the ADC consuming 40% less power than the nominal power mode.

FD/HD (SDO)

For flex I/O configuration, this control applies only if the SPI bus is disabled. FD/HD (SDO) is latched during the

rising edge of RESET.

Logic low setting identifies that the DUT flex I/O port will be configured for half-duplex operation.

12/24 (IFACE2) is also latched during the rising edge of RESET to identify interleaved data mode or parallel

data mode.

Logic low indicates that the flex I/O will configure itself for parallel data mode.

Logic high indicates that the flex I/O will configure itself for interleaved data mode.

12/ 24

For flex I/O configuration, the 12/24 pin control applies only if the SPI bus is disabled and the device is

configured for HD mode. 12/24 is latched during the rising edge of RESET.

12/24 (IFACE2) is used to identify interleaved data mode or parallel data modes.

Logic low indicates that the flex I/O will configure itself for HD24 mode.

Logic high indicates that the flex I/O will configure itself for HD12 mode.

SPI_Bus_Enable (SPI_CS)

SPI_CS is latched during the rising edge of RESET.

Logic low results in the SPI being disabled; SPI_DIO, SPI_CLK, and SPI_SDO act as mode pins configuration pins.

Logic high results in the SPI being fully operational; some mode pins will be disabled.

Interp0 and Interp1

Interpolation/PLL Factor Configuration. This control applies only if the SPI bus is disabled.

SPI_DIO (Interp1) and SPI_CLK (Interp0) configure the Tx path for 1× [00], 2× [01], or 4× [10] interpolation and

also enable the PLL of the same multiplication factor.

RxPWRDWN

Power-Down Control. RxPWRDWN logic level controls the power-down function of the Rx path.

Logic low results in the Rx path operating at normal power levels.

Logic high disables the ADC clock and disables some bias circuitry to reduce power consumption.

TxPWRDWN

Power-Down Control. TxPWRDWN logic level controls the power-down function of the Tx path.

Logic low results in the Tx path operating at normal power levels.

Logic high disables the DAC clocks and disables some bias circuitry to reduce power consumption.

Tx/Rx

Power-Down Control. Tx/Rx pin enables the appropriate Tx or Rx path in the half-duplex mode.

Logic low disables the Tx path and enables the Rx path.

Logic high disables the Rx path and enables the Tx path.