AD5044 datasheet(15/24 Pages) AD

15 / 24 page

AD5066

Rev. A | Page 15 of 24

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

The AD5066 is a quad 16-bit, serial input, voltage output

nanoDAC. The part operates from supply voltages of 2.7 V to

5.5 V. Data is written to the AD5066 in a 32-bit word format via

a 3-wire serial interface. The AD5066 incorporates a power-on

reset circuit to ensure the DAC output powers up to a known

output state. The devices also have a software power-down mode

that reduces the typical current consumption to typically 400 nA.

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by

















REFIN

OUT

where:

D is the decimal equivalent of the binary code that is loaded to

the DAC register (0 to 65,535).

N is the DAC resolution.

DAC ARCHITECTURE

The DAC architecture of the AD5066 consists of two matched

DAC sections. A simplified circuit diagram is shown in

Figure 39. The four MSBs of the 16-bit data word are decoded

to drive 15 switches, E1 to E15. Each of these switches connects

one of 15 matched resistors to either GND or the VREF

buffer

output. The remaining 12 bits of the data word drive the S0 to

S11 switches of a 12-bit voltage mode R-2R ladder network.

VREF

S11

E15

VOUT

12-BIT R-2R LADDER

FOUR MSBs DECODED

INTO 15 EQUAL

SEGMENTS

Figure 39. DAC Ladder Structure

REFERENCE BUFFER

The AD5066 operates with an external reference. Each of the

four on-board DACs has a dedicated voltage reference pin that

is buffered. The reference input pin has an input range of 2 V

to VDD − 0.4 V. This input voltage is then used to provide a

buffered reference for the DAC core.

SERIAL INTERFACE

The AD5066 has a 3-wire serial interface (SYNC, SCLK, and

DIN) that is compatible with SPI, QSPI, MICROWIRE, and

most DSP interface standards. See Figure 2 for a timing diagram

of a typical write sequence.

INPUT SHIFT REGISTER

The input shift register is 32 bits wide (see Figure 40). The first

four bits are don’t cares. The next four bits are the command

bits, C3 to C0 (see Table 7), followed by the 4-bit DAC address

bits, A3 to A0 (see Table 8), and finally the bit data-word. The

data-word comprises of a 16-bit input code followed by four don’t

care bits (see Figure 40). These data bits are transferred to the

Input register on the 32nd falling edge of SCLK. Commands can

be executed on individually selected DAC channels or on all DACs.

Table 7. Command Definitions

Command

Description

Write to Input Register n

Transfer contents of Input Register n to

DAC Register n

Write to Input Register n and update all

DAC Registers

Write to Input Register n and update

DAC Register n

Power down/power up DAC

Load clear code register

Load LDAC register

Reset (power-on reset)

Reserved

Table 8. DAC Input Register Address Bits

Address (n)

Selected DAC Channel

DAC A

DAC B

DAC C

DAC D

All DACs

ADDRESS BITS

COMMAND BITS

A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB31 (MSB)

DB0 (LSB)

DATA BITS

Figure 40. Input Shift Register Content

AD5044 Datasheet(PDF) 15 Page - Analog Devices

AD5044 Datasheet(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL