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AD5066

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CLEAR CODE REGISTER

The AD5066 has a hardware CLR pin that is an asynchronous

clear input. The CLR input is falling edge sensitive. Bringing the

CLR line low clears the contents of the input register and the

DAC registers to the data contained in the user-configurable

CLR register and sets the analog outputs accordingly (see

Table 11). This function can be used in system calibration to

load zero scale, midscale, or full scale to all channels together.

These clear code values are user-programmable by setting two

bits, Bit DB1 and Bit DB0, in the control register (see Table 11).

The default setting clears the outputs to 0 V. Command 0101 is

reserved for loading the clear code register (see Table 7).

Table 11. Clear Code Register

DB1 (CR1)

DB0 (CR0)

Clears to Code

0x0000

0x8000

0xFFFF

No operation

The part exits clear code mode on the 32nd falling edge of the

next write to the part. If CLR is activated during a write

sequence, the write is aborted.

The CLR pulse activation time (the falling edge of CLR to when

the output starts to change) is typically 10.6 µs. See Table 13 for

contents of the input shift register during the loading clear code

LDAC FUNCTION

Hardware LDAC Pin

The outputs of all DACs can be updated simultaneously using

the hardware LDAC pin, as shown in Figure 2. There are two

methods of using the hardware LDAC pin: synchronously

(LDAC permanently low) and asynchronously (LDAC pulsed).

Synchronous LDAC: LDAC is held permanently low. After new

data is read, the DAC registers are updated on the falling edge

of the 32nd SCLK pulse, provided LDAC is held low.

Asynchronous LDAC: LDAC is held high then pulsed low to

update. The outputs are not updated at the same time that the

input registers are written to. When LDAC is pulsed low, the

DAC registers are updated with the contents of the input

registers.

Command 0001, 0010 and 0011 (see Table 7) update the DAC

Software LDAC Function

Writing to the DAC using Command 0110 loads the 4-bit

LDAC register (DB3 to DB0). The default for each channel is

0; that is, the LDAC pin works normally. Setting the bits to 1

updates the DAC channel regardless of the state of the hardware

LDAC pin, so that it effectively sees the hardware LDAC pin

as being tied low (see Table 12 for the LDAC register mode of

operation.) This flexibility is useful in applications where the

user wants to simultaneously update select channels while the

remainder of the channels are synchronously updating.

Table 12. Load LDAC

LDAC Bits

(DB3 to

DB0)

LDAC

LDAC Operation

1/0

Determined by LDAC pin

DAC channels update, overrides the LDAC

pin; DAC channels see LDAC as 0

1 X = don’t care.

The LDAC register gives the user extra flexibility and control

over the hardware LDAC pin (see Table 14). Setting the LDAC

bits (DB0 to DB3) to 0 for a DAC channel means that this

channel’s update is controlled by the hardware LDAC pin.

Table 13. 32-Bit Input Shift Register Contents for Clear Code Function

MSB

LSB

DB31 to DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB2 to DB19

DB1

DB0

1/0

Don’t cares

Command bits (C3 to C0)

Address bits (A3 to A0)

Don’t cares

Clear code register

(CR1 to CR0)

Table 14. 32-Bit Input Shift Register Contents for LDAC

MSB

Overwrite Function

LSB

DB31

to DB28

DB27

DB26

DB25

DB24

DB23 to DB20

DB4

to DB19

DB3

DB2

DB1

DB0

DAC D

DAC C

DAC B

DAC A

Don’t cares

Command bits (C3 to C0)

Address bits (A3 to A0)—don’t cares

Don’t cares

Setting LDAC bit to 1 override LDAC pin

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