AD5044 datasheet(20/24 Pages) AD

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AD5066

Rev. A | Page 20 of 24

AD5066 to 80C51/80L51 Interface

Figure 45 shows a serial interface between the AD5066 and the

80C51/80L51 microcontroller. The setup for the interface is as

follows: TxD of the 80C51/80L51 drives SCLK of the AD5066,

RxD drives DIN on the AD5066, and a bit-programmable pin on

the port (P3.3) drives the SYNC signal. When data is to be

transmitted to the AD5066, P3.3 is taken low. The 80C51/80L51

transmit data in 8-bit bytes only; thus, only eight falling clock

edges occur in the transmit cycle. To load data to the DAC, P3.3

is left low after the first eight bits are transmitted, and a second,

third, and fourth write cycle is initiated to transmit the second,

third, and fourth byte of data. P3.3 is taken high following the

completion of this cycle. The 80C51/80L51 output the serial

data in a format that has the LSB first. The AD5066 must

receive data with the MSB first. The 80C51/80L51 transmit

routine should take this into account.

AD5066*

SYNC

P3.3

SCLK

TxD

DIN

RxD

*ADDITIONAL PINS OMITTED FOR CLARITY.

80C51/80L51*

Figure 45. AD5066 to 80C512/80L51 Interface

AD5066 to MICROWIRE Interface

Figure 46 shows an interface between the AD5066 and any

MICROWIRE-compatible device. Serial data is clocked into

the AD5066 on the falling edge of the SCLK.

AD5066*

SYNC

DIN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY.

MICROWIRE*

Figure 46. AD5066 to MICROWIRE Interface

AD5044 Datasheet(PDF) 20 Page - Analog Devices