FXLC95000CL datasheet(30/38 Pages) FREESCALE

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3. Set-up time in slave-transmitter mode is 1 system-clock period (16 MHz = 62.5 ns). There is no FIFO on the I2C.

4. A fast-mode, I2C bus device can be used in a standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal.

According to the standard mode, I2C bus specification, if such a device stretches the LOW period of the SCL signal, it

must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns before the SCL line is released.

5.11.3 SPI interfaces (slave and master)

Figure 11 and Table 14 describe the timing requirements for the SPI system.

(input)

SCLK

(input)

MOSI

(input)

MISO

(output)

Note:

Not defined—normally the MSB of the character just received.

SLAVE MSB OUT

BIT 6...1

SLAVE LSB OUT

Not defined

(see note)

LSB IN

MSB IN

BIT 6...1

Figure 11. Slave and master SPI timing

Table 14. Slave and master SPI timing

Drawing

Number

Function

Symbol

Min

Max

Unit

—

Operating frequency

fop

FOPH/4

SCLK period

tSCLK

—

tCYCH

Enable lead time

tLead

0.5

—

tCYCH

Enable lag time

tLag

0.5

—

tCYCH

Clock (SCLK) high or low time

tWSCLK

200

—

Table continues on the next page...

Mechanical and Electrical Specifications

Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.

Freescale Semiconductor, Inc.

FXLC95000CL Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

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