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AD7862

–4–

REV. 0

WARNING!

ESD SENSITIVE DEVICE

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7862 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

TIMING CHARACTERISTICS1, 2

A, B

Parameter

Versions

Version

Units

Test Conditions/Comments

tCONV

3.6

µs max

Conversion Time

tACQ

0.3

us max

Acquisition Time

Parallel Interface

ns min

to RD Setup Time

ns min

to RD Hold Time

ns min

CONVST

Pulse Width

ns min

Read Pulse Width

ns min

Data Access Time After Falling Edge of RD

ns max

ns min

Bus Relinquish Time After Rising Edge of RD

ns max

ns min

Time Between Consecutive Reads

NOTES

1Sample tested at +25

°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.

2 See Figure 1.

3Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.0 V.

4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then

extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus

relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications subject to change without notice.

(VDD = +5 V

5%, AGND = DGND = 0 V, REF = Internal. All Specifications TMIN to TMAX unless

otherwise noted.)

VA1

VA2

VB1

VB2

CONV

CONVST

BUSY

DATA

.........

Figure 1. Timing Diagram

+1.6V

1.6mA

200µA

50pF

OUTPUT

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

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