AD7851ARS datasheet(15/36 Pages) AD

15 / 36 page

–15–

REV. B

AD7851

CIRCUIT INFORMATION

The AD7851 is a fast, 14-bit single-supply ADC. The part

requires an external 6/7 MHz master clock (CLKIN), two

CREF capacitors, a CONVST signal to start conversion, and

power supply decoupling capacitors. The part provides the user

with track-and-hold, on-chip reference, calibration features,

ADC, and serial interface logic functions on a single chip. The

ADC section of the AD7851 consists of a conventional succes-

sive approximation converter based around a capacitor DAC.

The AD7851 accepts an analog input range of 0 V to +VDD

where the reference can be tied to VDD. The reference input to

the part is buffered on-chip.

A major advantage of the AD7851 is that a conversion can be

initiated in software as well as applying a signal to the

CONVST

pin. Another innovative feature of the AD7851 is self-calibration

on power-up, which is initiated having a capacitor from the

CAL pin to AGND, to give superior dc accuracy (see the

Automatic Calibration on Power-On section). The part is avail-

able in a 24-lead SSOP package which offers the user consider-

able space-saving advantages over alternative solutions.

CONVERTER DETAILS

The master clock for the part must be applied to the CLKIN

pin. Conversion is initiated on the AD7851 by pulsing the

CONVST input or by writing to the control register and setting

the

CONVST bit to 1. On the rising edge of CONVST (or at

the end of the control register write operation), the on-chip

track-and-hold goes from track to hold mode. The falling edge

of the CLKIN signal which follows the rising edge of the

CONVST signal initiates the conversion, provided the rising

edge of

CONVST occurs at least 10 ns typically before this

CLKIN edge. The conversion cycle will take 18.5 CLKIN peri-

ods from this CLKIN falling edge. If the 10 ns setup time is not

met, the conversion will take 19.5 CLKIN periods. The maxi-

AVDD

DVDD

AIN(+)

AIN(–)

AMODE

CREF1

CREF2

SLEEP

DIN

DOUT

SYNC

SM1

SM2

CONVST

AGND

DGND

CLKIN

SCLK

REFIN/REFOUT

POLARITY

AD7851

ANALOG (5V)

SUPPLY

0.01 F

0.1 F

10 F

DVDD

UNIPOLAR RANGE

0.01 F

SERIAL MODE

SELECTION BITS

MASTER

CLOCK

INPUT

CONVERSION

START INPUT

FRAME SYNC OUTPUT

SERIAL DATA OUTPUT

0.1 F

CAL

AUTO CAL ON

POWER-UP

INTERNAL/

EXTERNAL

REFERENCE

0V TO VREF

INPUT

7MHz/6MHz

OSCILLATOR

SERIAL CLOCK OUTPUT

DVDD

333kHz/285kHz PULSE

GENERATOR

OPTIONAL

EXTERNAL

REFERENCE

AD1584/REF198

0.01 F

ANALOG (5V)

SUPPLY

0.1 F

10 F

DIN AT DGND

=> NO WRITING

TO DEVICE

0.1 F

470nF

CH1

CH2

CH3

CH4

OSCILLOSCOPE

2 LEADING ZEROS

FOR ADC DATA

Figure 10. Typical Circuit

mum specified conversion time is 3.25

µs (6 MHz ) and 2.8 µs

(7 MHz) for the A and K Grades, respectively, for the AD7851

(19.5 tCLKIN, CLKIN = 6 MHz/7 MHz). When a conversion is

completed, the BUSY output goes low, and then the result of

the conversion can be read by accessing the data through the

edge of serial interface. To obtain optimum performance from

the part, the read operation should not occur during the conver-

sion or 500 ns prior to the next

CONVST rising edge. How-

ever, the maximum throughput rates are achieved by reading/

writing during conversion, and reading/writing during conver-

sion is likely to degrade the signal-to-(noise + distortion) by

only 0.5 dBs. The AD7851 can operate at throughput rates up

to 333 kHz. For the AD7851, a conversion takes 19.5 CLKIN

periods; 2 CLKIN periods are needed for the acquisition time

giving a full cycle time of 3.59

µs (= 279 kHz, CLKIN = 6 MHz)

for the K grade and 3.08

µs (= 325 kHz, CLKIN = 7 MHz) for

the A grade.

TYPICAL CONNECTION DIAGRAM

Figure 10 shows a typical connection diagram for the AD7851.

The DIN line is tied to DGND so that no data is written to the

part. The AGND and the DGND pins are connected together

at the device for good noise suppression. The

CAL pin has a

0.01

µF capacitor to enable an automatic self-calibration on

power-up. The SCLK and

SYNC are configured as outputs by

having SM1 and SM2 at DVDD. The conversion result is output

in a 16-bit word with 2 leading zeros followed by the MSB of

the 14-bit result. Note that after the AVDD and DVDD power up,

the part will require approximately 150 ms for the internal refer-

ence to settle and for the automatic calibration on power-up to

be completed.

For applications where power consumption is a major concern, the

SLEEP pin can be connected to DGND. (See the Power-Down

Options section for more detail on low power applications.)

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