APW7063 datasheet(15/22 Pages) ANPEC

15 / 22 page

Rev. A.10 - Aug., 2009

APW7063

www.anpec.com.tw

FESR

FLC

Frequency

-40dB/dec

-20dB/dec

Gain

Application Information (Cont.)

Figure 3. The LC Filter Gain & Frequency

The PWM modulator is shown in Figure 4. The input is

the output of the error amplifier and the output is the PHASE

node. The transfer function of the PWM modulator is given

by:

GAINPWM =

VOSC

PWM

Comparator

Driver

Output of

Error

Amplifier

VIN

PHASE

Figure 4. The PWM Modulator

The compensation circuit is shown in Figure 5. R3 and

C1 introduce a zero and C2 introduces a pole to reduce

the switching noise. The transfer function of error ampli-

fier is given by:

GAINAMP =

























sC2

sC1

The pole and zero of the compensation network are:

FP =

Compensation (Cont.)

OSC

∆

























V OUT

E rror

Am plifier

V REF

COMP

Figure 5. Compensation Network

The closed loop gain of the converter can be written as:

GAINLC x GAINPWM x

x GAINAMP

Figure 6 shows the converter gain and the following guide-

lines will help to design the compensation network.

1.Select the desired zero crossover frequency FO:

(1/5 ~ 1/10) x FS >FO>FZ

Use the following equation to calculate R3:

ESR

OSC

∆

Where:

gm = 900

µA/V

2.Place the zero FZ before the LC filter double poles

FLC:

FZ = 0.75 x FLC

Calculate the C1 by the equation:

0.75

3. Set the pole at the half the switching frequency:

FP = 0.5xFS

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