APW8722C datasheet(15/23 Pages) ANPEC

15 / 23 page

Rev. A.3 - Jun., 2013

www.anpec.com.tw

APW8722/A/B/C/D

Application Information

Output Voltage Selection

The output voltage can be programmed with a resistive

divider. Use 1% or better resistors for the resistive divider

is recommended. The FB pin is the inverter input of the

error amplifier, and the reference voltage is 0.6V. The

output voltage is determined by:

Where R1 is the resistor connected from V

OUT to FB and

R2 is the resistor connected from FB to the GND.









OUT

0.6

Output Capacitor Selection

The selection of C

OUT is determined by the required effec-

tive series resistance (ESR) and voltage rating rather than

the actual capacitance requirement. Therefore, selecting

high performance low ESR capacitors is intended for

switching regulator applications. In some applications,

multiple capacitors have to be paralleled to achieve the

desired ESR value. If tantalum capacitors are used, make

sure they are surge tested by the manufactures. If in doubt,

consult the capacitors manufacturer.

Input Capacitor Selection

The input capacitor is chosen based on the voltage rat-

ing and the RMS current rating. For reliable operation,

select the capacitor voltage rating to be at least 1.3 times

higher than the maximum input voltage. The maximum

RMS current rating requirement is approximately I

OUT/2

where I

OUT is the load current. During power up, the input

capacitors have to handle large amount of surge current.

If tantalum capacitors are used, make sure they are surge

tested by the manufactures. If in doubt, consult the ca-

pacitors manufacturer.

For high frequency decoupling, a ceramic capacitor be-

tween 0.1

µF to 1µF can connect between VCC and ground

pin.

Inductor Selection

The inductance of the inductor is determined by the out-

put voltage requirement. The larger the inductance, the

lower the inductor’s current ripple. This will translate into

lower output ripple voltage. The ripple current and ripple

voltage can be approximated by:

where Fs is the switching frequency of the regulator.

∆V

OUT = IRIPPLE x ESR

OUT

RIPPLE

−

A tradeoff exists between the inductor’s ripple current and

the regulator load transient response time. A smaller in-

ductor will give the regulator a faster load transient re-

sponse at the expense of higher ripple current and vice

versa. The maximum ripple current occurs at the maxi-

mum input voltage. A good starting point is to choose the

ripple current to be approximately 30% of the maximum

output current.

Once the inductance value has been chosen, selecting

an inductor is capable of carrying the required peak cur-

rent without going into saturation. In some types of

inductors, especially core that is make of ferrite, the ripple

current will increase abruptly when it saturates. This will

result in a larger output ripple voltage.

PWM Compensation

The output LC filter of a step down converter introduces a

double pole, which contributes with -40dB/decade gain

slope and 180 degrees phase shift in the control loop. A

compensation network among COMP, FB, and V

OUT

should be added. The compensation network is shown in

Figure 5. The output LC filter consists of the output induc-

tor and output capacitors. The transfer function of the LC

filter is given by:

The F

LC is the double poles of the LC filter, and FESR is the

zero introduced by the ESR of the output capacitor.

PHASE

OUT

ESR

Figure 2. The Output LC Filter

OUT

ESR

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