APW8819 datasheet(18/28 Pages) ANPEC

18 / 28 page

Rev. A.6 - May, 2013

APW8819

www.anpec.com.tw

Function Description (Cont.)

PWM Converter Current-Limit

The current-limit circuit employs a “valley” current-sens-

ing algorithm (See Figure 2). The APW8819 uses the

low-side MOSFET’s R

DS(ON) of the synchronous rectifier

as a current-sensing element. If the magnitude of the

current-sense signal at PHASE pin is above the current

limit threshold, the PWM is not allowed to initiate a new

cycle. The actual peak current is greater than the current

limit threshold by an amount equals to the inductor ripple

current. Therefore, the exact current-limit characteristic

and maximum load capability are the functions of the

sense resistance, inductor value, and input voltage.

The PWM controller uses the low-side MOSFET’s on-

resistance R

DS(ON) to monitor the current for protection

against shortened outputs. The MOSFET’s R

DS(ON) is var-

ied by temperature and gate to source voltage, the user

should determine the maximum R

DS(ON) in manufacture’s

datasheet.

The OC pin can source 10

µA through an external resistor

for adjusting current-limit threshold. The voltage at OC

pin is equal to 10

µA x R

OC. The relationship between the

sampled voltage V

OC and the current-limit threshold ILIMIT

is given by:

Where R

OC is the resistor of current-limit setting threshold.

DS(ON) is the low side MOSFETs conducive resistance.

ILIMIT is the setting current-limit threshold. I

LIMIT can be

expressed as I

OUT minus half of peak-to-peak inductor

current.

The PCB layout guidelines should ensure that noise and

DC errors do not corrupt the current-sense signals at

PHASE. Place the hottest power MOSEFTs as close to

the IC as possible for best thermal coupling. When com-

bined with the under-voltage protection circuit, this cur-

rent-limit method is effective in almost every circumstance.

DS(ON)

LIMIT

Figure 2. Current-Limit Algorithm

VTT Sink/Source Regulator

The output voltage at VTT pin tracks the reference voltage

applied at VTTREF pin. Two internal N-channel MOSFETs

controlled by separate high bandwidth error amplifiers

regulate the output voltage by sourcing current from

VLDOIN pin or sinking current to GND pin. To prevent two

pass transistors from shoot-through, a small voltage off-

set is created between the positive inputs of the two error

amplifiers. The VTT with fast response feedback loop

keeps tracking to the VTTREF within ±40mV at all condi-

tions including fast load transient.

S3, S5 Control

In the DDR2/DDR3 memory applications, it is important

to keep VDDQ always higher than VTT/VTTREF including

both start-up and shutdown.

The S3 and S5 signals control the VDDQ, VTT, VTTREF

states and these pins should be connected to SLP_S3

and SLP_S5 signals respectively. The table1 shows the

truth table of the S3 and S5 pins. When both S3 and S5

are above the logic threshold voltage, the VDDQ, VTT and

VTTREF are turned on at S0 state. When S3 is low and

S5 is high, the VDDQ and VTTREF are kept on while the

VTT voltage is disabled and left high impedance in S3

state. When both S3 and S5 are low, the VDDQ, VTT and

VTTREF are turned off and discharged to the ground ac-

cording to the discharge mode selected by MODE pin

during S4/S5 state.

Time

LIMIT

PEAK

VALLEY

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