APA2121 datasheet(21/27 Pages) ANPEC

21 / 27 page

Rev. A.4 - Jul., 2013

APA2120/2121

www.anpec.com.tw

• To enable the HP(headphone) inputs, set HP/LINE

pin to a high level.

As APA2121, HP/LINE input multiplexor and SE/BTL out-

put operating mode have independent control paths,

which can be used for multiple audio input system. This

function will be the same as APA2120 when HP/LINE and

SE/BTL are tied together.

• To select the LINE inputs, set HP/LINE pin to a low

level.

Application Information (Cont.)

Input HP/LINE Operation (Cont.)

This logic-low voltage at the SE/BTL pin makes APA2120

into LINE input mode operation. It becomes HP input

mode when phonejack plugged.

An internal multiplexor selects the input to connect to the

amplifier based on the state of the HP/LINE pin of the

APA2121.

PC-BEEP Detection

APA2120/1 integrate a BEEP detect circuit for NOTEBOOK

PC. When BEEP signal is provided on the PCBEEP input

pin, the BEEP mode is active. APA2120/1 will force to BTL

mode and the internal gain is fixed at -10dB. The PCBEEP

signal becomes the amplifier input signal and plays on

the speaker without coupling capacitor. It will be out of

shutdown mode whenever BEEP mode is enabled.

APA2120/1 will return to previous setting when it is out of

BEEP mode. The input impedance is 100k

Ω on the

PCBEEP input pin.

APA2120 provide extra PCBEN control input signal to force

IC into BEEP mode. The BEEP mode will be enabled

when PCBEN goes to a high level. When the BEEP mode

is overridden, the signal from the PCBEEP will pass to

speaker directly.

Clock Generator

APA2120/1 integrate a clock block to avoid volume con-

trol function abnormal when VOLUME control signal with

spike or noise. APA2120/1 change each step of volume

gain after four clock cycles make sure control signal ready.

It provides 130kHz frequency if no capacitor is placed on

CLK pin to the ground. The larger capacitance will slow

down the and clock frequency. A capacitor 33nF between

CLK to the ground and will generate 147Hz frequency on

the CLK pin.

BTL Amplifier Efficiency

An easy-to-use equation to calculate efficiency starts out

as being equal to the ratio of power from the power sup-

ply to the power delivered to the load.

The following equations are the basis for calculating

amplifier efficiency.

Where :

PSUP

Efficiency

(9)

PO =

VORMS x VORMS

2RL

VPxVP

VORMS = √2

(10)

(11)

PSUP = VDD x IDDAVG = VDD x 2VP

πRL

Table 1 Calculates Efficiencies for Four Different Output

Power Levels.

Note that the efficiency of the amplifier is quite low for

lower power levels and rises sharply as power to the load

is increased resulting in a nearly flat internal power dissi-

pation over the normal operating range. Note that the in-

ternal dissipation at full output power is less than the

dissipation in the half power range. Calculating the effi-

ciency for a specific system is the key to proper power

supply design. For a stereo 1W audio system with 8

Ω

loads and a 5V supply, the maximum draw on the power

supply is almost 3W.

A final point to remember about linear amplifiers (either

SE or BTL) is how to manipulate the terms in the effi-

ciency equation to an utmost advantage when possible.

Note that in equation, V

DD is in the denominator. This indi-

cates that as V

DD goes down, efficiency goes up. In other

words, use the efficiency analysis to choose the correct

supply voltage and speaker impedance for the application.

Po (W)

Efficiency (%)

IDD(A)

VPP(V)

PD (W)

0.25

31.25

0.16

2.00

0.55

0.50

47.62

0.21

2.83

0.55

1.00

66.67

0.30

4.00

0.5

1.25

78.13

0.32

4.47

0.35

**High peak voltages cause the THD to increase.

Table 1. Efficiency Vs Output Power in 5-V/8

Ω BTL

Systems

APA2121 Datasheet(PDF) 21 Page - Anpec Electronics Coropration

APA2121 Datasheet(HTML) 21 Page - Anpec Electronics Coropration

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

Datasheet Download

Link URL