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Date: 3/6/06

SP6656, 400mA Synchronous Buck Regulator with Dynamically Adjustable Voltage Output

© Copyright 2006 Sipex Corporation

timer. The minimum on-timer times out and

indicates DRVON can be reset if the voltage

regulation point RESET is held low until

one-shot is triggered to blank the loop com-

parator from starting a new charge cycle for

a minimum period. This blanking period

occurs during the noisy LX transition to

discharge, where spurious comparator

loop is in a discharge or wait state until the

loop comparator starts the next charge cycle

by DRVON going high.

If an over current occurs during charge the

loop is interrupted and DRVON is RESET.

The off-time one-shot pulse width is wid-

loop in discharge for that time. At the end of

the off-time the loop is released and con-

trolled by VOLOW. In this manner maxi-

mum inductor current is controlled on a

cycle-by-cycle basis. An assertion of UVLO

(undervoltage lockout) or TSD (thermal shut-

down) holds the loop in no-charge until the

fault has ended.

On-Time Control - Discharge Phase

The discharge phase follows with the high

side PMOS switch opening and the low side

NMOS switch closing to provide a discharge

path for the inductor current. The decreas-

ing inductor current and the load current

cause the output voltage to drop. Under

normal load conditions when the inductor

current is below the programmed limit, the

off-time will continue until the output voltage

falls below the regulation threshold, which

initiates a new charge cycle via the loop

comparator.

The inductor current “floats” in continuous

conduction mode. During this mode the

inductor peak current is below the pro-

grammed limit and the valley current is

above zero. This is to satisfy load currents

that are greater than half the minimum cur-

by the equation:

*

L

where:

L = Inductor value

fies to:

L

For most applications, the inductor current

ripple controlled by the SP6656 is constant

regardless of input and output voltage.

The maximum loop frequency in CCM is

defined by the equation:

where:

Ignoring conduction losses simplifies the

loop frequency to:

1

*

AND’ing the loop comparator and the on-

timer reduces the switching frequency for

load currents below half the inductor ripple

current. This increases light load efficiency.

The minimum on-time insures that the in-

more than the load current demands. The

converter goes in to a standard pulse fre-

quency modulation (PFM) mode where the

switching frequency is proportional to the

load current.

THEORY OF OPERATION