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SP6656 Datasheet(PDF) 14 Page - Sipex Corporation |
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SP6656 Datasheet(HTML) 14 Page - Sipex Corporation |
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14 / 16 page ![]() 14 Date: 3/6/06 SP6656, 400mA Synchronous Buck Regulator with Dynamically Adjustable Voltage Output © Copyright 2006 Sipex Corporation APPLICATION INFORMATION Output Voltage Ripple Frequency An important consideration in a power sup- ply application is the frequency value of the output ripple. Given the control technique of the SP6656 (as described in the operations section), the frequency of the output ripple will vary when in light to moderate load in the discontinuous or PFM mode. For mod- erate to heavy loads greater than about 100mA inductor current ripple, (for the typi- cal 10µH inductor application on 100mA is half the 200mA inductor current ripple), the output ripple frequency will be fairly con- stant. From the operations section, this maxi- mum loop frequency in continuous conduc- tion mode is FLP ≈ 1 VOUT (VIN - VOUT) KON * VIN * Data for loop frequency, as measured from output voltage ripple frequency, can be found in the typical performance curves. Layout Considerations Proper layout of the power and control circuits is necessary in a switching power supply to obtain good output regulation with stability and a minimum of output noise. The SP6656 application circuit can be made very small and reside close to the IC for best performance and solution size, as long as some layout techniques are taken into consideration. To avoid excessive interference between the SP6656 high frequency converter and the other active components on the board, some rules should be followed. Refer to the typical application schematic on page 1 and the sample PCB layout shown in the following figures to illustrate how to layout a SP6656 power supply. Avoid injecting noise into the sensitive part of circuit via the ground plane. Input and output capacitors conduct high frequency current through the ground plane. Separate the con- trol and power grounds and connect them together at a single point. Power ground plane is shown in the figure titled PCB top sample layout and connects the ground of the COUT capacitor to the ground of the CIN capacitor and then to the PGND pin 10. The control ground plane connects from pin 9 GND to ground of the CVIN capacitor and the RI ground return of the feedback resistor. These two separate control and power ground planes come together in the figure titled PCB top sample layout where SP6656 pin 9 GND is connected to pin 10 PGND. Power loops on the input and output of the converter should be laid out with the shortest and widest traces possible. The longer and narrower the trace, the higher the resistance and inductance it will have. The length of traces in series with the capacitors increases its ESR and ESL and reduces their effective- ness at high frequencies. Therefore, put the 1µF bypass capacitor as close to the VIN and GND pins of the converter as possible, the 10µF CIN close to the PVIN pin and the 10µF output capacitor as close to the inductor as possible. The external voltage feedback net- work RF, RI, RS and feedforward capacitor CF should be placed very close to the FB pin. Any noise traces like the LX pin should be kept away from the voltage feedback network and separated from it by using power ground copper to minimize EMI. |
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