AD9833 datasheet(13/24 Pages) AD

13 / 24 page

Data Sheet

AD9833

Rev. E | Page 13 of 24

FUNCTIONAL DESCRIPTION

SERIAL INTERFACE

The AD9833 has a standard 3-wire serial interface that is

compatible with the SPI, QSPI™, MICROWIRE®, and DSP

interface standards.

Data is loaded into the device as a 16-bit word under the

control of a serial clock input, SCLK. The timing diagram for

this operation is given in .

The FSYNC input is a level-triggered input that acts as a frame

synchronization and chip enable. Data can be transferred into the

device only when FSYNC is low. To start the serial data transfer,

FSYNC should be taken low, observing the minimum FSYNC-

to-SCLK falling edge setup time, t7. After FSYNC goes low, serial

data is shifted into the input shift register of the device on the

falling edges of SCLK for 16 clock pulses. FSYNC may be taken

high after the 16th falling edge of SCLK, observing the minimum

SCLK falling edge to FSYNC rising edge time, t8. Alternatively,

FSYNC can be kept low for a multiple of 16 SCLK pulses and

then brought high at the end of the data transfer. In this way, a

continuous stream of 16-bit words can be loaded while FSYNC

is held low; FSYNC goes high only after the 16th SCLK falling

edge of the last word loaded.

The SCLK can be continuous, or it can idle high or low between

write operations. In either case, it must be high when FSYNC

goes low (t11).

For an example of how to program the AD9833, see the AN-1070

Application Note on the Analog Devices, Inc., website.

POWERING UP THE AD9833

The flowchart in Figure 26 shows the operating routine for the

AD9833. When the AD9833 is powered up, the part should be

reset. This resets the appropriate internal registers to 0 to provide

an analog output of midscale.

To avoid spurious DAC outputs during AD9833 initialization,

the reset bit should be set to 1 until the part is ready to begin

generating an output. A reset does not reset the phase, frequency,

or control registers. These registers will contain invalid data and,

therefore, should be set to known values by the user. The reset

bit should then be set to 0 to begin generating an output. The

data appears on the DAC output seven or eight MCLK cycles

after the reset bit is set to 0.

LATENCY PERIOD

A latency period is associated with each asynchronous write

operation in the AD9833. If a selected frequency or phase

or eight MCLK cycles before the analog output changes. The

delay can be seven or eight cycles, depending on the position

of the MCLK rising edge when the data is loaded into the

destination register.

CONTROL REGISTER

The AD9833 contains a 16-bit control register that allows the

user to configure the operation of the AD9833. All control bits

other than the mode bit are sampled on the internal falling edge

of MCLK.

Table 6 describes the individual bits of the control register.

The different functions and the various output options of

the AD9833 are described in more detail in the Frequency and

Phase Registers section.

To inform the AD9833 that the contents of the control register

will be altered, D15 and D14 must be set to 0, as shown in Table 5.

Table 5. Control Register Bits

D15

D14

D13

Control Bits

SIN

ROM

PHASE

ACCUMULATOR

(28-BIT)

AD9833

(LOW POWER)

10-BIT DAC

MUX

SLEEP12

SLEEP1

RESET

MODE + OPBITEN

DIV2

OPBITEN

VOUT

MUX

DIGITAL

OUTPUT

(ENABLE)

DIVIDE

BY 2

DB15

DB14

DB13

B28

DB12

HLB

DB11

FSELECT

DB10

PSELECT

DB9

DB8

RESET

DB7

SLEEP1

DB6

SLEEP12

DB5

OPBITEN

DB4

DB3

DIV2

DB2

DB1

MODE

DB0

Figure 24. Function of Control Bits

AD9833 Datasheet(PDF) 13 Page - Analog Devices

AD9833 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL