REV. C

ADSP-21065L

–32–

Serial Ports

Parameter

Min

Max

Unit

External Clock

Timing Requirements:

TFS/RFS Setup Before TCLK/RCLK

1

4.0

ns

TFS/RFS Hold After TCLK/RCLK

1

4.0

ns

Receive Data Setup Before RCLK

1

1.5

ns

Receive Data Hold After RCLK

1

4.0

ns

TCLK/RCLK Width

9.0

ns

TCLK/RCLK Period

ns

Internal Clock

Timing Requirements:

TFS Setup Before TCLK

8.0

ns

TFS/RFS Hold After TCLK/RCLK

1

1.0

ns

Receive Data Setup Before RCLK

1

3.0

ns

Receive Data Hold After RCLK

1

3.0

ns

External or Internal Clock

Switching Characteristics:

RFS Delay After RCLK (Internally Generated RFS)

2

13.0

ns

RFS Hold After RCLK (Internally Generated RFS)

2

3.0

ns

External Clock

Switching Characteristics:

TFS Delay After TCLK (Internally Generated TFS)

2

13.0

ns

TFS Hold After TCLK (Internally Generated TFS)

2

3.0

ns

Transmit Data Delay After TCLK

2

12.5

ns

Transmit Data Hold After TCLK

2

4.0

ns

Internal Clock

Switching Characteristics:

TFS Delay After TCLK (Internally Generated TFS)

2

4.5

ns

TFS Hold After TCLK (Internally Generated TFS)

2

–1.5

ns

Transmit Data Delay After TCLK

2

7.5

ns

Transmit Data Hold After TCLK

2

0.0

ns

TCLK/RCLK Width

ns

Enable and Three-State

Switching Characteristics:

Data Enable from External TCLK

2

5.0

ns

Data Disable from External RCLK

2

10.0

ns

Data Enable from Internal TCLK

2

0.0

ns

Data Disable from Internal TCLK

2

3.0

ns

TCLK/RCLK Delay from CLKIN

18.0 + 6 DT

ns

SPORT Disable After CLKIN

14.0

ns

External Late Frame Sync

Data Delay from Late External TFS or External RFS

with MCE = 1, MFD = 0

3, 4

10.5

ns

Data Enable from late FS or MCE = 1, MFD = 0

3, 4

3.5

ns

Data Delay from TCLK/RCLK for Late External

TFS or External RFS with MCE = 1, MFD = 0

3, 4

12.0

ns

Data Enable from RCLK/TCLK for Late External FS or

MCE = 1, MFD = 0

3, 4

4.5

ns

NOTES

To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame

sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.

*Word selected timing for I