REV. C

ADSP-21065L

–16–

Memory Read—Bus Master

Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.

These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching

characteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these

timing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin

timing requirements as described in the note below.

Parameter

Min

Max

Unit

Timing Requirements:

Address, Selects Delay to Data Valid

1, 2

28.0 + 32 DT + W

ns

24.0 + 26 DT + W

ns

Data Hold from Address Selects

3

0.0

ns

Data Hold from

0.0

ns

ACK Delay from Address, Selects

2, 3

24.0 + 30 DT + W

ns

ACK Delay from

19.5 + 24 DT + W

ns

Switching Characteristics:

Address, Selects Hold After

RD High

–1.0 + H

ns

Address, Selects to

3.0 + 6 DT

ns

RD Pulsewidth

25.0 + 26 DT + W

ns

RD High to WR, RD Low

4.5 + 6 DT + HI

ns

RD High to DMAGx Low

11.0 +12 DT + HI

ns

W = (number of wait states specified in WAIT register)

NOTES

MSx, SW, BMS, are referenced.

(Both, after internal wait states have completed).

WR

ACK

DATA

RD

ADDRESS

MSx , SW

BMS

DMAG

Figure 11. Memory Read—Bus Master