REV. C

ADSP-21065L

–20–

Synchronous Read/Write—Bus Slave

Use these specifications for ADSP-21065L bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor

memory space). The bus master must meet these (bus slave) timing requirements.

Parameter

Min

Max

Unit

Timing Requirements:

Address,

SW Setup Before CLKIN

24.5 + 25 DT

ns

Address,

SW Hold Before CLKIN

4.0 + 8 DT

ns

21.0 + 21 DT

ns

RD/WR Low Hold After CLKIN

–2.50 – 5 DT

7.5 + 7 DT

ns

RD/WR Pulse High

2.5

ns

Data Setup Before

WR High

4.5

ns

Data Hold After

WR High

0.0

ns

Switching Characteristics:

Data Delay After CLKIN

31.75 + 21 DT

ns

Data Disable After CLKIN

2

1.0 – 2 DT

7.0 – 2 DT

ns

ACK Delay After CLKIN

29.5 + 20 DT

ns

ACK Disable After CLKIN

2

1.0 – 2 DT

6.0 – 2 DT

ns

NOTES

For two ADSP-21065Ls to communicate synchronously as master and slave, certain master and slave specification combinations

must be satisfied. Do not compare specification values directly to calculate master/slave clock skew margins for those specifications

listed below. The following table shows the appropriate clock skew margin.

Table IV. Bus Master to Slave Skew Margins

Master Specification

Slave Specification

Skew Margin

+ 2.25 ns

+ 1.50 ns

+ 3.00 ns

+ 2.25 ns

N/A

+ 2.75 ns

+ 1.50 ns

+ 1.25 ns

N/A

3.00 ns

N/A

3.75 ns