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PE97022 Datasheet(PDF) 6 Page - Peregrine Semiconductor |
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PE97022 Datasheet(HTML) 6 Page - Peregrine Semiconductor |
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6 / 14 page  Product Specification PE97022 Page 6 of 14 ©2010-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0235-07 │ UltraCMOS® RFIC Solutions Table 6. AC Characteristics: VDD = 3.3 V, -40 °C < TA < 85 °C, unless otherwise specified Notes: 1. Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk specification. 2. CMOS logic levels can be used to drive the reference input. If the VDD of the CMOS driver matches the VDD of PLL IC, then the reference input can be DC coupled. Otherwise, the reference input should be AC coupled. 3. Parameter is guaranteed through characterization only and is not tested. 4. Parameters below are not tested for die sales. These parameters are verified during the element evaluation. Symbol Parameter Conditions Min Typical Max Units Control Interface and Latches (see Figures 4, 5, 6) fClk Serial data clock frequency (Note 1) 10 MHz tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns tDSU Sdata set-up time after Sclk rising edge, D[7:0] set-up time to M1_WR, M2_WR, A_WR, E_WR rising edge 10 ns tDHLD Sdata hold time after Sclk rising edge, D[7:0] hold time to M1_WR, M2_WR, A_WR, E_WR rising edge 10 ns tPW S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width 30 ns tCWR Sclk rising edge to S_WR rising edge. S_WR, M1_WR, M2_WR, A_WR falling edge to Hop_WR rising edge 30 ns tCE Sclk falling edge to E_WR transition 30 ns tWRC S_WR falling edge to Sclk rising edge. Hop_WR fall- ing edge to S_WR, M1_WR, M2_WR, A_WR rising edge 30 ns tEC E_WR transition to Sclk rising edge 30 ns tMDO MSEL data out delay after Fin rising edge CL = 12 pf 8 ns Main Divider (Including Prescaler)4 PFin Input level range External AC coupling 275 MHz ≤Freq ≤3200MHz -5 5 dBm External AC coupling 3.2 GHz < Freq ≤3.5 GHz 3.15 V ≤VDD ≤3.45 V 0 5 dBm Main Divider (Prescaler Bypassed)4 Fin Operating frequency 50 300 MHz PFin Input level range External AC coupling -5 5 dBm Reference Divider fr Operating frequency (Note 3) 100 MHz Pfr Reference input power2 Single-ended input -2 10 dBm Phase Detector fc Comparison frequency (Note 3) 50 MHz SSB Phase Noise (Fin = 1.9 GHz, fr = 20 MHz, fc = 20 MHz, LBW = 50 kHz, VDD = 3.3 V, Temp = 25 C)4 N Phase Noise 100 Hz Offset -89 dBc/Hz N Phase Noise 1 kHz Offset -95 dBc/Hz N Phase Noise 10 kHz Offset -102 dBc/Hz SSB Phase Noise (Fin = 1.9 GHz, fr = 20 MHz, fc = 20 MHz, LBW = 50 kHz, VDD = 3.0 V, Temp = 25 C)4 N Phase Noise 100 Hz Offset -87 dBc/Hz N Phase Noise 1 kHz Offset -94 dBc/Hz N Phase Noise 10 kHz Offset -101 dBc/Hz |
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