1

Motorola TMOS Power MOSFET Transistor Device Data

Designer's™ Data Sheet

Power Field Effect Transistor

N–Channel Enhancement–Mode Silicon Gate

This high voltage MOSFET uses an advanced termination

scheme to provide enhanced voltage–blocking capability without

degrading performance over time. In addition, this advanced TMOS

E–FET is designed to withstand high energy in the avalanche and

commutation modes. The new energy efficient design also offers a

drain–to–source diode with a fast recovery time. Designed for high

voltage, high speed switching applications in power supplies,

converters and PWM motor controls, these devices are particularly

well suited for bridge circuits where diode speed and commutating

safe operating areas are critical and offer additional safety margin

against unexpected voltage transients.

• Robust High Voltage Termination

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a Discrete

Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• IDSS and VDS(on) Specified at Elevated Temperature

Rating

Symbol

Value

Unit

Drain–to–Source Voltage

VDSS

600

Vdc

Drain–to–Gate Voltage (RGS = 1.0 MΩ)

VDGR

600

Vdc

Gate–to–Source Voltage — Continuous

— Single Pulse (tp ≤ 50 µs)

VGS

±20

±40

Vdc

Drain Current

— Continuous

— Single Pulse (tp ≤ 10 µs)

ID

IDM

2.0

9.0

Adc

Total Power Dissipation

Derate above 25

°C

PD

50

0.4

Watts

W/

°C

Operating and Storage Temperature Range

TJ, Tstg

– 55 to 150

°C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 50 Vdc, VGS = 10 Vdc, L = 95 mH, RG = 25 Ω, Peak IL = 2.0 Adc)

EAS

190

mJ

Thermal Resistance — Junction to Case

°

— Junction to Ambient

°

R

θJC

R

θJA

2.5

°

62.5

°

°C/W

Maximum Lead Temperature for Soldering Purposes, 1/8

″ from case for 10 seconds

TL

260

°C

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit

curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Order this document

by MTP2N60E/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

© Motorola, Inc. 1996

MTP2N60E

TMOS POWER FET

2.0 AMPERES

600 VOLTS

RDS(on) = 3.8 OHMS

Motorola Preferred Device

®

D

S

G

CASE 221A–06, Style 5

TO–220AB