DMVA3 datasheet(86/287 Pages) TI1

86 / 287 page

DMVA3, DMVA4

SPRS872B – MAY 2013 – REVISED DECEMBER 2013

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3.3.16 PCI Express (PCIe)

Table 3-34. PCI Express (PCIe) Terminal Functions

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

PCIE_RXN0

PCIE Receive Data Lane 0. When the PCIe SERDES are I

J30

powered down, these pins should be left unconnected.

PCIE_RXP0

PCIE Receive Data Lane 0. When the PCIe SERDES are I

K30

powered down, these pins should be left unconnected.

PCIE_TXN0

PCIE Transmit Data Lane 0. When the PCIe SERDES

K31

are powered down, these pins should be left

unconnected.

PCIE_TXP0

PCIE Transmit Data Lane 0. When the PCIe SERDES

L31

are powered down, these pins should be left

unconnected.

SERDES_CLKN

PCIE Serdes Reference Clock Inputs and optional SATA

H31

Reference Clock Inputs. When PCIe is not used, and

these pins are not used as optional SATA Reference

Clock Inputs, these pins can be left unconnected.

SERDES_CLKP

PCIE Serdes Reference Clock Inputs and optional SATA

H30

Reference Clock Inputs. When PCIe is not used, and

these pins are not used as optional SATA Reference

Clock Inputs, these pins can be left unconnected.

Device Pins

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