3933

THREE-PHASE POWER

MOSFET CONTROLLER

www.allegromicro.com

Terminal

Name

1

PGND

2

RESET

3GLC

4SC

5

GHC

6CC

7GLB

8SB

9

GHB

10

CB

11

GLA

12

SA

13

GHA

14

CA

15

V

CCOUT

16

LCAP

17

FAULT

18

MODE

19

20

H1

21

H3

22

H2

23

DIR

24

BRAKE

25

BRKCAP

26

BRKSEL

27

PWM

28

RC

29

SENSE

30

REF

31

DEAD

32

AGND

RESET — A logic input used to enable the device, internally

pulled up to V

device and force all gate drivers to 0 V, coasting the motor. A

logic LOW allows the gate drive to follow commutation logic.

This input overrides BRAKE.

GLA/GLB/GLC — Low-side, gate-drive outputs for external

NMOS drivers. External series-gate resistors (as close as

possible to the NMOS gate) can be used to control the slew rate

seen at the power-driver gate, thereby controlling the di/dt and

dv/dt of the SA/SB/SC outputs. Each output is designed and

specified to drive a 1000 pF load with a rise time of 50 ns.

SA/SB/SC — Directly connected to the motor, these terminals

sense the voltages switched across the load. These terminals

are also connected to the negative side of the bootstrap capaci-

tors and are the negative supply connections for the floating

high-side drive.

GHA/GHB/GHC — High-side, gate-drive outputs for external

NMOS drivers. External series-gate resistors (as close as

possible to the NMOS gate) can be used to control the slew rate

seen at the power-driver gate, thereby controlling the di/dt and

dv/dt of the SA/SB/SC outputs. Each output is designed and

specified to drive a 1000 pF load with a rise time of 100 ns.

CA/CB/CC — High-side connections for the bootstrap capaci-

tors, positive supply for high-side gate drive. The bootstrap

associated output SA/SB/SC terminal is low. When the output

swings high, the voltage on this terminal rises with the output to

provide the boosted gate voltage needed for n-channel power

FETs.

Terminal Descriptions

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