Hiccup Mode off-time

Soft-Start

Restart delay

1V

2V

4V

Count to Eight

1V

LM5046

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SNVS703G – FEBRUARY 2011 – REVISED MARCH 2013

voltage is ramped between 4.0V and 2.0V eight times.

•

When the counter reaches eight, the RES pin voltage is pulled low and the soft-start capacitor is released to

begin a soft-start sequence. The SS capacitor voltage slowly increases. When the SS voltage reaches 1.0V,

the PWM comparator will produce the first narrow pulse.

•

If the overload condition persists after restart, cycle-by-cycle current limiting will begin to increase the voltage

on the RES capacitor again, repeating the hiccup mode sequence.

•

If the overload condition no longer exists after restart, the RES pin will be held at ground by the 5

μA current

sink and the normal operation resumes.

The hiccup mode function can be completely disabled by connecting the RES pin to the AGND pin. In this

configuration the cycle-by-cycle protection will limit the maximum output current indefinitely, no hiccup restart

sequences will occur.

Figure 13. Hiccup Mode Delay and Soft-Start Timing Diagram

PWM Comparator

The LM5046 pulse width modulator (PWM) comparator is a three input device, it compares the signal at the

RAMP pin to the loop error signal or the soft-start, whichever is lower, to control the duty cycle. This comparator

is optimized for speed in order to achieve minimum controllable duty cycles. The loop error signal is received

from the external feedback and isolation circuit in the form of a control current into the COMP pin. The COMP pin

current is internally mirrored by a matching pair of NPN transistors which sink current through a 5k

Ω resistor

connected to the 5V reference. The resulting control voltage passes through a 1V offset, followed by a 2:1

resistor divider before being applied to the PWM comparator.

An opto-coupler detector can be connected between the REF pin and the COMP pin. Because the COMP pin is

controlled by a current input, the potential difference across the opto-coupler detector is nearly constant. The

bandwidth limiting phase delay which is normally introduced by the significant capacitance of the opto-coupler is

thereby greatly reduced. Higher loop bandwidths can be realized since the bandwidth limiting pole associated

with the opto-coupler is now at a much higher frequency. The PWM comparator polarity is configured such that

with no current flowing into the COMP pin, the controller produces maximum duty cycle.

RAMP Pin

The voltage at the RAMP pin provides the modulation ramp for the PWM comparator. The PWM comparator

compares the modulation ramp signal at the RAMP pin to the loop error signal to control the duty cycle. The

modulation ramp signal can be implemented either as a ramp proportional to the input voltage, known as feed-

forward voltage mode control, or as a ramp proportional to the primary current, known as current mode control.

The ability to configure the RAMP pin for either voltage mode or current mode allows the controller to be

implemented for the optimum control method depending upon the design constraints. Refer to the APPLICATION

INFORMATION section for more details on configuring the RAMP pin for feed-forward voltage mode control and

peak current mode control.

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