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MP2932 Datasheet(PDF) 12 Page - Monolithic Power Systems

Part # MP2932
Description  6-Phase PWM Controller with 8-Bit DAC Code for VR10 and VR11
PDF  23 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP2932 Datasheet(HTML) 12 Page - Monolithic Power Systems

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MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE
MP2932 Rev.1.02
www.MonolithicPower.com
12
4/30/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
FB
R
ISEN
R
X
R
N
OUT
I
OFS
V
REF
V
OUT
V
(7)
Where VREF is the reference voltage, VOFS is the
programmed offset voltage, IOUT is the total
output current of the converter, RISEN is the
sense resistor connected to the ISEN+ pin, and
RFB is the feedback resistor, N is the active
channel number, and RX is the DCR, or RSENSE
depending on the sensing method.
Therefore, the loadline is defined as:
ISEN
R
X
R
N
FB
R
LL
R
(8)
Output Voltage Offset Programming
In Figure 5, OFS pin is used to generate no-
load offset. A resistor RREF between DAC and
REF is selected, and the product (IOFS x ROFS) is
equal to the desired offset voltage.
R
C
FB
DAC
VCC
OR
GND
R
REF
OFS
GND
VCC
1.6V
0.4V
DYNAMIC
ID D/A
E/A
MP2932
REF
REF
OFS
Figure 5—Offset Voltage Programming
Connect a resistor ROFS between OFS to VCC
to generate a positive offset. The voltage
across it is regulated to 1.6V. This causes a
proportional current (IOFS) to flow into OFS. The
positive offset is:
OFS
R
REF
R
1.6
OFFSET
V
(9)
Connect a resistor ROFS between OFS to GND
to generate a negative offset. The voltage
across it is regulated to 0.4V, and IOFS flows out
of OFS. The negative offset is:
OFS
R
REF
R
0.4
OFFSET
V
(10)
Enable and Disable
While in shutdown mode, the PWM outputs are
held in a Hi-Z state, and the SD signal is pulled
low to assure the Intelli-phase remain off. The
following input conditions must be met to start
MP2932.
1. VCC must reach the internal power-on reset
(POR) rising threshold.
2. EN_PWR is used to coordinate the power
sequencing between VCC and another
voltage rail. The enable comparator holds
the MP2932 in shutdown until the voltage at
EN_PWR rises above 0.875V.
3. The voltage on EN_VTT must be higher than
0.875V to enable the controller. This pin is
typically connected to the output of VTT VR.
4.
10kO
910O
MP2932 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
EN_PWR
ENABLE
COMPARATOR
0.875V
0.875V
EN_VTT
POR
CIRCUIT
+12V
SOFT-START
AND
FAULT LOGIC
Figure 6—Power Sequencing Using
Threshold Sensitive Enable (EN) Function
When all conditions are satisfied, MP2932
begins the soft-start and ramps the output
voltage to 1.1V first. After remaining at 1.1V for
some time, MP2932 reads the ID code at ID
input pins. If the ID code is valid, MP2932 will
regulate the output to the final ID setting. If the
ID code is OFF code, MP2932 will shutdown,
and cycling VCC, EN_PWR or EN_VTT is
needed to restart.



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