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MP7770 Datasheet(PDF) 18 Page - Monolithic Power Systems

Part # MP7770
Description  2 x 45W Stereo Single-Ended or 90W Mono BTL Class-D Audio Amplifier
PDF  23 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP7770 Datasheet(HTML) 18 Page - Monolithic Power Systems

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MP7770 –2 X 45W STEREO SE OR 90W MONO BTL CLASS D AUDIO AMPLIFIER
MP7770 Rev.1.0
www.MonolithicPower.com
18
12/4/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
to the MP7770 while blocking the DC voltage.
Choose an input coupling capacitor such that
the corner frequency (fIN) is less than the
passband frequency. The corner frequency is
calculated as:
IN
IN
IN
C
R
2
1
f
Timer capacitor
The start-up source current slew rate is
adjusted from the timing capacitor, CTIMER: The
larger the CTIMER capacitance is, the smaller the
start-up current slew rate is. Select a CTIMER
value larger than 312nF, so the start-up current
slew rate would be smaller than 20mA/50ms
which helps eliminate the turn-on pop. The
recommended 2.2μF capacitor CTIMER results in
a start-up current slew rate of approximately
20mA/350ms.
Power Source
For maximum output power, the amplifier circuit
requires a regulated external power source. A
high power-supply voltage can deliver more
power to a given load resistance, but a power-
source voltage exceeding the maximum voltage
of 36V can damage the MP7770. The
MP7770’s power supply rejection is excellent,
though power-supply noise can pass to the
output, so care must be taken to minimize
power supply noise within the pass-band
frequencies. Bypass the power supply with a
large capacitor (typically aluminum electrolytic)
along with a smaller 1μF ceramic capacitor at
the MP7770 VDD supply pins.
PCB Layout
Circuit layout is critical for optimal performance,
low output distortion, and noise. Duplicate the
EVB layout for best results. For layout changes,
follow these guidelines and use Figure 8 as SE
layout references, use Figure 9 as BTL layout
reference.
1) Place the following components as close to
the MP7770 as possible:
Bootstrap Capacitors
CBS1 and CBS2 supply the gate drive current to
the internal HS-FET. Place CBS1 as close to
BST1/2 pin and SW1/2 pin as possible.
Likewise, place CBS2 as close to BST2 pin and
SW2 pins as possible.
Power Supply Bypass Capacitors
CBYP1 and CBYP2 carry the transient current for
the
switching
power
stage.
To
avoid
overstressing the MP7770 and excessive
output noise, place CBYP1 as close to the VDD1
pins and PGND1 pins as possible, and place
CBYP2 as close to the VDD2 pins and PGND2
pins as possible.
Integral Capacitors
CINT sets the amplifier switching frequencies
and are typically on the order of a few nF. Place
the integral capacitor CINT as close to the
corresponding input as possible to reduce
distortion and noise. For example, place CINT1
as close to pins 2 and 3 as possible at SE
output configuration.
Reference Bypass Capacitors for SE Output
When used with SE output, CR1 and CR2 filter
the ½ VDD reference voltages. Place CR1 and
CR2 as close to the IC as possible to improve
power supply rejection and reduce distortion
and noise at the output.
2) The Inductor-Capacitor (LC) filter converts
the pulse train at SW to the output voltage that
drives the speaker. Please keep the filter
capacitor close to the inductor.
3) Keep the sensitive feedback signal trace on
the input side and shield the trace with the
AGND plane. Make sure that any traces
carrying the switch node (SW) voltages are
routed far from any input signal traces. If the
trace must run near the SW trace near the
input, shield the input with a ground plane
between the traces. Physically separate each
channel
to



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