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PCI1520PDVG4 Datasheet(PDF) 49 Page - Texas Instruments |
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PCI1520PDVG4 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 139 page  3−14 Table 3−7. Register- and Bit-Loading Map EEPROM OFFSET REGISTER OFFSET REGISTER BITS LOADED FROM EEPROM 00h Flag 01h: Load / FFh: do not load 01h PCI 04h Command register, bits 8, 6−5, 2−0 Note: bits loaded per following: b8 ← b7 b6 ← b6 b5 ← b5 b2 ← b2 b1 ← b1 b0 ← b0 02h PCI 40h Subsystem vendor ID bits 7−0 ← bits 7−0 03h PCI 40h Subsystem vendor ID bits 15−8 ← bit 7−0 04h PCI 42h Subsystem ID bits 7−0 ← bits 7−0 05h PCI 42h Subsystem ID bits 15−8 ← bits 7−0 06h PCI 44h PC Card 16-bit I/F legacy-mode base address bits 7−1 ← bits 7−1 07h PCI 44h PC Card 16-bit I/F legacy-mode base address bits 15−8 ← bits 7−0 08h PCI 44h PC Card 16-bit I/F legacy-mode base address bit 23:16 ← bit 7:0 09h PCI 44h PC Card 16-bit I/F legacy-mode base address bits 31−24 ← bits 7−0 0Ah PCI 80h System control bits 7−0 ← bits 7−0 0Bh PCI 80h System control bits 15−8 ← bits 7−0 0Ch PCI 80h System control byte bits 31−24 ← bits 7−0 0Dh PCI 8Ch Multifunction routing bits 7−0 ← bits 7−0 0Eh PCI 8Ch Multifunction routing bits 15−8 ← bits 7−0 0Fh PCI 8Ch Multifunction routing bits 23−16 ← bits 7−0 10h PCI 8Ch Multifunction routing bits 27−24 ← bits 3−0 11h PCI 90h Retry status bits 7, 6 ← bits 7, 6 12h PCI 91h Card control bits 7, 5 ← bits 7, 6 13h PCI 92h Device control bits 6, 3−0 ← bits 6, 3−0 14h PCI 93h Diagnostic bits 7, 4−0 ← bits 7, 4−0 15h PCI A2h Power management capabilities bit 15 ← bit 7 16h ExCA 00h ExCA identification and revision bits 7−0 ← bits 7−0 17h CB Socket + 0Ch (function 0) Function 0 socket force event, bit 27 ← bit 3 18h CB Socket + 0Ch (function 1) Function 1 socket force event, bit 27 ← bit 3 This format must be followed for the PCI1520 to load initializations from a serial EEPROM. All bit fields must be considered when programming the EEPROM. The serial EEPROM is addressed at slave address 1010 000b by the PCI1520. All hardware address bits for the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample application circuit (Figure 3−8) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND. 3.6.4 Accessing Serial-Bus Devices Through Software The PCI1520 provides a programming mechanism to control serial bus devices through software. The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−8 lists the registers used to program a serial-bus device through software. |
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