PCI1520PDVG4 datasheet(87/139 Pages) TI

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4−26

4.37 Power-Management Capabilities Register

This register contains information on the capabilities of the PC Card function related to power management. Both

PCI1520 CardBus bridge functions support D0, D1, D2, and D3 power states. See Table 4−14 for a complete

description of the register contents.

Bit

Name

Power-management capabilities

Type

Default

Power-management capabilities

Offset:

A2h

Type:

Read/Write, Read-only

Default:

FE12h

Table 4−14. Power-Management Capabilities Register Description

BIT

SIGNAL

TYPE

FUNCTION

PME support. This 5-bit field indicates the power states from which the PCI1520 device functions may

assert PME. A 0 (zero) for any bit indicates that the function cannot assert the PME signal while in that

power state. These five bits return 11111b when read. Each of these bits is described below:

PME_Support

Bit 15 defaults to the value 1 indicating the PME signal can be asserted from the D3cold state. This bit is

R/W because wake-up support from D3cold is contingent on the system providing an auxiliary power source

to the VCC terminals. If the system designer chooses not to provide an auxiliary power source to the VCC

terminals for D3cold wake-up support, then BIOS should write a 0 to this bit.

14−11

PME_Support

Bit 14 contains the value 1, indicating that the PME signal can be asserted from D3hot state.

Bit 13 contains the value 1, indicating that the PME signal can be asserted from D2 state.

Bit 12 contains the value 1, indicating that the PME signal can be asserted from D1 state.

Bit 11 contains the value 1, indicating that the PME signal can be asserted from the D0 state.

D2_Support

D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device

power state.

D1_Support

D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device

power state.

8−6

RSVD

Reserved. Bits 8−6 return 0s when read.

DSI

Device-specific initialization. Bit 5 returns 1 when read, indicating that the CardBus controller function

requires special initialization (beyond the standard PCI configuration header) before the generic-class

device driver is able to use it.

AUX_PWR

Auxiliary power source. Bit 4 is meaningful only if bit 15 (PME_Support, D3cold) is set. When bit 4 is set,

it indicates that support for PME in D3cold requires auxiliary power supplied by the system by way of a

proprietary delivery vehicle. When bit 4 is 0, it indicates that the function supplies its own auxiliary power

source.

PMECLK

PME clock. Bit 3 returns 0 when read, indicating that no host bus clock is required for the PCI1520 to

generate PME.

2−0

VERSION

Version. Bits 2−0 return 010b when read, indicating that the power-management registers (PCI offsets

A4h−A7h, see Sections 4.38−4.40) are defined in the PCI Bus Power Management Interface Specification

version 1.1.

PCI1520PDVG4 Datasheet(PDF) 87 Page - Texas Instruments

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