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MP28259 Datasheet(PDF) 10 Page - Monolithic Power Systems

Part # MP28259
Description  High Efficiency, Fast Transient, 2A, 4.2V-20V Input Synchronous Step-down Converter in QFN12
PDF  18 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP28259 Datasheet(HTML) 10 Page - Monolithic Power Systems

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MP28259 – 2A, 4.2V-20V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER
MP28259 Rev. 1.34
www.MonolithicPower.com
10
4/27/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
The device reverts to PWM mode once the
output current exceeds the critical level. After that,
the switching frequency stays fairly constant over
the output current range.
BST
N1
LSG
VCC
C2
SW
L
COUT
C5
Figure 4—
Floating Driver and Bootstrap Charging
The floating power MOSFET driver is powered by
an external bootstrap capacitor. This floating
driver has its own UVLO protection with a rising
threshold of 2.2V and a hysteresis of 150mV.
The bootstrap capacitor is charges from VCC
through N1 (Fig. 4). N1 turns on when the LS-
FET turns on and turns off when the LS-FET
turns off.
Switching Frequency
MP28259 uses constant-on-time (COT) control
because there is no dedicated oscillator in the IC.
The input voltage is feed-forwarded to the on-
time one-shot timer through the resistor R7. The
duty ratio is kept as VOUT/VIN, and the switching
frequency is fairly constant over the input voltage
range.
The switching frequency can be
determined with the following equation:
6
SW
FREQ
IN
DELAY
IN
OUT
10
F(kHz)
9.3 R
(k )
V(V)
T(ns)
V(V) 0.4
V
(V)
=
×Ω
×+
−
(3)
Where TDELAY is the comparator delay, and
equals approximately 40ns.
MP28259 is optimized to operate at high
switching frequency with high efficiency. High
switching frequency makes it possible to use
small-sized LC filter components to save system
PCB space.
Jitter and FB Ramp Slope
Jitter occurs in both PWM and skip modes when
noise in the VFB ripple propagates a delay to the
HS-FET driver, as shown in Figures 5 and 6.
Jitter can affect system stability, with noise
immunity proportional to the steepness of VFB’s
downward slope. However, VFB ripple does not
directly affect noise immunity.
V
RE F
V
FB
HS D river
VNOISE
J itter
V
S L O PE1
Figure 5—Jitter in PWM Mode
V
FB
HS D river
Jitter
V
REF
V
SL O P E 2
VNOISE
Figure 6—Jitter in Skip Mode
Ramp with Large ESR Cap
In the case of POSCAP or other types of
capacitor with larger ESR is applied as output
capacitor. The ESR ripple dominates the output
ripple, and the slope on the FB is quite ESR
related. Figure 7 shows an equivalent circuit in
PWM mode with the HS-FET off and without an
external ramp circuit. Turn to application
information section for design steps with large
ESR caps.
Figure 7—Simplified Circuit in PWM Mode
without
External
Ramp
Compensation



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