AD7713 datasheet(12/28 Pages) AD

12 / 28 page

REV. D

–12–

AD7713

Figures 2a and 2b gives similar information to that outlined in

Table I. In this plot, the output rms noise is shown for the full

range of available cutoff frequencies rather than for some typical

cutoff frequencies as in Tables I and II. The numbers given in

these plots are typical values at 25

°C.

GAIN OF 1

GAIN OF 2

GAIN OF 4

GAIN OF 8

0.1

1.0

1000.0

100.0

10.0

10000.0

100

10k

NOTCH FREQUENCY (Hz)

Figure 2a. Plot of Output Noise vs. Gain and Notch

Frequency (Gains of 1 to 8)

GAIN OF 16

GAIN OF 32

GAIN OF 64

GAIN OF 128

0.1

1.0

100.0

10.0

1000.0

100

10k

NOTCH FREQUENCY (Hz)

Figure 2b. Plot of Output Noise vs. Gain and Notch

Frequency (Gains of 16 to 128)

CIRCUIT DESCRIPTION

The AD7713 is a -

ADC with on-chip digital filtering, intended

for the measurement of wide dynamic range, low frequency signals,

such as those in industrial control or process control applications. It

contains a

(or charge balancing) ADC, a calibration

microcontroller with on-chip static RAM, a clock oscillator, a

digital filter, and a bidirectional serial communications port.

The part contains three analog input channels, two program-

mable gain differential input channels, and one programmable

gain high-level single-ended input channel. The gain range on

both inputs is from 1 to 128. For the AIN1 and AIN2 inputs,

this means that the input can accept unipolar signals of between

0 mV to 20 mV and 0 V to 2.5 V or bipolar signals in the range

from

±20 mV to ±2.5 V when the reference input voltage equals

2.5 V. The input voltage range for the AIN3 input is 4

VREF/

GAIN and is 0 V to 10 V with the nominal reference of 2.5 V and

a ANALOG gain of 1. The input signal to the selected analog

input channel is continuously sampled at a rate determined by

the frequency of the master clock, MCLK IN, and the selected

gain (see Table III). A charge balancing ADC ( -

modulator)

converts the sampled signal into a digital pulse train whose duty

cycle contains the digital information. The programmable gain

function on the analog input is also incorporated in this -

modulator with the input sampling frequency being modified to

give the higher gains. A sinc

3 digital low-pass filter processes the

output of the

modulator and updates the output register at

a rate determined by the first notch frequency of this filter. The

output data can be read from the serial port randomly or peri-

odically at any rate up to the output register update rate. The

first notch of this digital filter (and therefore its –3 dB frequency)

can be programmed via an on-chip control register. The

programmable range for this first notch frequency is from

1.952 Hz to 205.59 Hz, giving a programmable range for the

–3 dB frequency of 0.52 Hz to 53.9 Hz.

The basic connection diagram for the part is shown in Figure 3.

This shows the AD7713 in the external clocking mode with

both the AVDD and DVDD pins of the AD7713 being driven

from the analog 5 V supply. Some applications will have sepa-

rate supplies for both AVDD and DVDD, and in some of these

cases, the analog supply will exceed the 5 V digital supply (see the

Power Supplies and Grounding section).

REF IN(+)

AIN1(+)

AIN1(–)

AIN3

AVDD

DVDD

AGND

DGND

MCLK IN

MCLK OUT

REF IN(–)

ANALOG 5V

SUPPLY

0.1 F

10 F

AD7713

DIFFERENTIAL

ANALOG INPUT

SINGLE-ENDED

ANALOG INPUT

ANALOG

GROUND

DIGITAL

GROUND

MODE

DVDD

STANDBY

DVDD

AIN2(+)

AIN2(–)

2.5V

REFERENCE

DRDY

DATA

READY

TFS

TRANSMIT

(WRITE)

RFS

RECEIVE

(READ)

SDATA

SERIAL

DATA

SCLK

SERIAL

CLOCK

ADDRESS

INPUT

DIFFERENTIAL

ANALOG INPUT

SYNC

Figure 3. Basic Connection Diagram

The AD7713 provides a number of calibration options that can

be programmed via the on-chip control register. A calibration

cycle can be initiated at any time by writing to this control regis-

ter. The part can perform self-calibration using the on-chip

calibration microcontroller and SRAM to store calibration

parameters. Other system components may also be included in

the calibration loop to remove offset and gain errors in the input

channel using the system calibration mode. Another option is a

background calibration mode where the part continuously

performs self-calibration and updates the calibration coeffi-

cients. Once the part is in this mode, the user does not have to

worry about issuing periodic calibration commands to the device

or asking the device to recalibrate when there is a change in the

ambient temperature or power supply voltage.

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