AD7713 datasheet(19/28 Pages) AD

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REV. D

AD7713

–19–

word in the output register. If a new data-word becomes avail-

able to the output register while data is being read from the

output register,

DRDY will not indicate this and the new data-

word will be lost to the user.

DRDY is not affected by reading

from the control register or the calibration registers.

Data can be accessed from the output data register only when

DRDY is low. If RFS goes low with DRDY high, no data trans-

fer will take place.

DRDY does not have any effect on reading

data from the control register or from the calibration registers.

Figure 10 shows a timing diagram for reading from the AD7713

in the self-clocking mode. This read operation shows a read

from the AD7713’s output data register. A read from the con-

trol register or calibration registers is similar, but, in these cases,

the

DRDY line is not related to the read function. Depending

on the output update rate, it can go low at any stage in the

control/calibration register read cycle without affecting the read

and its status should be ignored. A read operation from either

the control or calibration registers must always read 24 bits of

data from the respective register.

Figure 10 shows a read operation from the AD7713. For the

timing diagram shown, it is assumed that there is a pull-up

resistor on the SCLK output. With

DRDY low, the RFS input

is brought low.

RFS going low enables the serial clock of the

AD7713 and also places the MSB of the word on the serial data

line. All subsequent data bits are clocked out on a high-to-low

transition of the serial clock and are valid prior to the following

rising edge of this clock. The final active falling edge of SCLK

clocks out the LSB, and this LSB is valid prior to the final active

rising edge of SCLK. Coincident with the next falling edge of

SCLK,

DRDY is reset high. DRDY going high turns off the

SCLK and the SDATA outputs, this means that the data hold

time for the LSB is slightly shorter than for all other bits.

Write Operation

Data can be written to either the control register or calibration

registers. In either case, the write operation is not affected by

the

DRDY line, and the write operation does not have any

effect on the status of

DRDY. A write operation to the control

the respective register.

Figure 11 shows a write operation to the AD7713. A0 determines

whether a write operation transfers data to the control register

or to the calibration registers. This A0 signal must remain valid

for the duration of the serial write operation. The falling edge of

TFS enables the internally generated SCLK output. The serial

data to be loaded to the AD7713 must be valid on the rising

edge of this SCLK signal. Data is clocked into the AD7713 on

the rising edge of the SCLK signal, with the MSB transferred

first. On the last active high time of SCLK, the LSB is loaded to

the AD7713. Subsequent to the next falling edge of SCLK, the

SCLK output is turned off. (The timing diagram of Figure 11

assumes a pull-up resistor on the SCLK line.)

External Clocking Mode

The AD7713 is configured for its external clocking mode by

tying the MODE pin low. In this mode, SCLK of the AD7713

is configured as an input, and an external serial clock must be

provided to this SCLK pin. This external clocking mode is

designed for direct interface to systems which provide a serial

clock output which is synchronized to the serial data output,

including microcontrollers, such as the 80C51, 87C51,

68HC11, and 68HC05, and most digital signal processors.

Read Operation

As with the self-clocking mode, data can be read from either the

output register, the control register, or the calibration registers.

A0 determines whether the data read accesses data from the

control register or from the output/calibration registers. This A0

THREE-STATE

SDATA (O)

SCLK (O)

RFS (I)

A0 (I)

DRDY (O)

MSB

LSB

t10

Figure 10. Self-Clocking Mode, Output Data Read Operation

SDATA (I)

SCLK (O)

TFS (I)

A0 (I)

MSB

LSB

t14

t15

t16

t17

t18

t19

t10

Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation

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