AD7713 datasheet(18/28 Pages) AD

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REV. D

–18–

AD7713

The amount of offset that can be accommodated depends on

whether the unipolar or bipolar mode is being used. This offset

range is limited by the requirement that the positive full-scale

calibration limit is

≤ 1.05

VREF/GAIN for AIN1 and AIN2.

Therefore, the offset range plus the span range cannot exceed

1.05

VREF/GAIN for AIN1 and AIN2. If the span is at its

minimum (0.8

VREF/GAIN), the maximum the offset can be

is (0.25

VREF/GAIN) for AIN1 and AIN2. For AIN3, both

ranges are multiplied by a factor of 4.

In the bipolar mode, the system offset calibration range is

again restricted by the span range. The span range of the

converter in bipolar mode is equidistant around the voltage

used for the zero-scale point, thus the offset range plus half

the span range cannot exceed (1.05

VREF/GAIN) for AIN1

and AIN2. If the span is set to 2

VREF/GAIN, the offset

span cannot move more than

± (0.05

VREF/GAIN) before

the endpoints of the transfer function exceed the input overrange

limits

±(1.05 V

REF/GAIN) for AIN1. If the span range is set to

the minimum

±(0.4

VREF/GAIN), the maximum allowable

offset range is

±(0.65 VREF/GAIN) for AIN1 and AIN2. The

AIN3 input can only be used in the unipolar mode.

POWER-UP AND CALIBRATION

On power-up, the AD7713 performs an internal reset, which

sets the contents of the control register to a known state. How-

ever, to ensure correct calibration for the device, a calibration

routine should be performed after power-up.

The power dissipation and temperature drift of the AD7713 are

low and no warm-up time is required before the initial calibra-

tion is performed. However, the external reference must have

stabilized before calibration is initiated.

Drift Considerations

The AD7713 uses chopper stabilization techniques to minimize

input offset drift. Charge injection in the analog switches and dc

leakage currents at the sampling node are the primary sources of

offset voltage drift in the converter. The dc input leakage cur-

rent is essentially independent of the selected gain. Gain drift

within the converter depends primarily upon the temperature

tracking of the internal capacitors. It is not affected by leakage

currents.

Measurement errors due to offset drift or gain drift can be elimi-

nated at any time by recalibrating the converter or by operating

the part in the background calibration mode. Using the system

calibration mode can also minimize offset and gain errors in the

signal conditioning circuitry. Integral and differential linearity

errors are not significantly affected by temperature changes.

POWER SUPPLIES AND GROUNDING

The analog and digital supplies to the AD7713 are independent

and separately pinned out to minimize coupling between the

analog and digital sections of the device. The digital filter will

provide rejection of broadband noise on the power supplies,

except at integer multiples of the modulator sampling frequency.

The digital supply (DVDD) must not exceed the analog positive

supply (AVDD) by more than 0.3 V. If separate analog and digital

supplies are used, the recommended decoupling scheme is shown

in Figure 9. In systems where AVDD = 5 V and DVDD = 5 V, it is

recommended that AVDD and DVDD are driven from the same 5 V

supply, although each supply should be decoupled separately as

shown in Figure 9. It is preferable that the common supply is the

system’s analog 5 V supply.

It is also important that power is applied to the AD7713 before

signals at REF IN, AIN, or the logic input pins in order to avoid

excessive current. If separate supplies are used for the AD7713 and

the system digital circuitry, then the AD7713 should be powered

up first. If it is not possible to guarantee this, then current limiting

resistors should be placed in series with the logic inputs.

AD7713

0.1 F

10 F

ANALOG

SUPPLY

DIGITAL 5V

SUPPLY

AVDD

DVDD

Figure 9. Recommended Decoupling Scheme

DIGITAL INTERFACE

The AD7713’s serial communications port provides a flexible

arrangement to allow easy interfacing to industry-standard

microprocessors, microcontrollers, and digital signal processors.

A serial read to the AD7713 can access data from the output

serial write to the AD7713 can write data to the control register

or the calibration registers.

Two different modes of operation are available, optimized for

different types of interface where the AD7713 can act either as

master in the system (it provides the serial clock) or as slave (an

external serial clock can be provided to the AD7713). These

two modes, labeled self-clocking mode and external clocking

mode, are discussed in detail in the following sections.

Self-Clocking Mode

The AD7713 is configured for its self-clocking mode by tying

the MODE pin high. In this mode, the AD7713 provides the

serial clock signal used for the transfer of data to and from the

AD7713. This self-clocking mode can be used with processors

that allow an external device to clock their serial port, including

most digital signal processors and microcontrollers, such as the

68HC11 and 68HC05. It also allows easy interfacing, to serial

parallel conversion circuits in systems with parallel data com-

munication, allowing interfacing to 74XX299 universal shift

registers without any additional decoding. In the case of shift

registers, the serial clock line should have a pull-down resistor

instead of the pull-up resistor shown in Figure 10 and Figure 11.

Read Operation

Data can be read from either the output register, the control

data read accesses data from the control register or from the

output/calibration registers. This A0 signal must remain valid for

the duration of the serial read operation. With A0 high, data is

accessed from either the output register or from the calibration

registers. With A0 low, data is accessed from the control register.

The function of the

DRDY line is dependent on only the output

update rate of the device and the reading of the output data

DRDY goes low when a new data-word is available in

the output data register. It is reset high when the last bit of data

(either 16th bit or 24th bit) is read from the output register. If

data is not read from the output register, the

DRDY line will

remain low. The output register will continue to be updated at

the output update rate, but

DRDY will not indicate this. A read

from the device in this circumstance will access the most recent

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