Specifications

All specifications apply to all models unless noted otherwise.

General specifications

Acquisition rate with frequency

margin

8 GT/s (+5% to -10%)

5 GT/s (±10%)

1.5 GT/s (±10%)

Number of lanes

TLA7SA08

8 differential inputs, x4

TLA7SA16

16 differential inputs, x8

Record length

160 M symbols translates into 160 ms at 8 GT/s, 320 ms at 5 GT/s, or 640 ms at 2.5 GT/s at 100% bus utilization.

TLA7SA08

160 M symbols per differential input, 4 GB physical memory total

TLA7SA16

160 M symbols per differential input, 8 GB physical memory total (16 GB physical memory for a x16 configuration)

Time stamp range

292 hours

Time stamp

50 bits at 936 ps resolution

Clocking/acquisition modes

TLA module without SSC

(spread spectrum clocking)

External reference clock

100 MHz ±10% with or without SSC

External reference clock

frequency tolerance

±300 ppm

Number of mainframe instrument

slots required per TLA series

module

2

Module configuration requirements

Bi-directional link widths per

module

Module

X1

X4

X8

X16

TLA7SA08

1

1

0

0

TLA7SA16

1

1

1

2

Input specifications (with P67SA00 series probes)

Capacitive loading

Please refer to the specifications in the Tektronix Logic Analyzer Solutions for PCI Express 3.0 manual, Tektronix part number,

077-0400-xx.

Minimum data eye

Please refer to the specifications in the Tektronix Logic Analyzer Solutions for PCI Express 3.0 manual, Tektronix part number,

077-0400-xx.

Datasheet

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