AM28F256A datasheet(7/35 Pages) AMD

7 / 35 page

Am28F256A

PIN DESCRIPTION

A0–A14

Address Inputs for memory locations. Internal latches

hold addresses during write cycles.

CE# (E#)

Chip Enable active low input activates the chip’s control

logic and input buffers. Chip Enable high will deselect

the device and operates the chip in stand-by mode.

DQ0-DQ7

Data Inputs during memory write cycles. Internal

latches hold data during write cycles. Data Outputs

during memory read cycles.

No Connect-corresponding pin is not connected

internally to the die.

OE# (G#)

Output Enable active low input gates the outputs of the

device through the data buffers during memory read

cycles. Output Enable is high during command

sequencing and program/erase operations.

VCC

Power supply for device operation. (5.0 V

± 5% or 10%)

VPP

Program voltage input. VPP must be at high voltage in

order to write to the command register. The command

ory array contents. Memory contents cannot be altered

when VPP ≤ VCC +2 V.

VSS

Ground.

WE# (W)

Write Enable active low input controls the write function

of the command register to the memory array. The target

address is latched on the falling edge of the Write En-

able pulse and the appropriate data is latched on the ris-

ing edge of the pulse. Write Enable high inhibits writing

to the device.

AM28F256A Datasheet(PDF) 7 Page - Advanced Micro Devices